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mb91f465ka mb91f465kb fr60, mb91460k series, 32-bit microcontroller datasheet cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04602 rev. *a revised april 14, 2016 mb91460k series is a line of general-pur pose 32-bit risc microcontrollers designed fo r embedded control applications which requ ire high-speed real-time processing, such as consumer devices and on- board vehicle systems. this series uses the fr60 cpu, which is compatible with the fr family of cpus. this series contains the lin-usart and can controllers. features fr60 cpu core 32-bit risc, load/store archit ecture, five-stage pipeline 16-bit fixed-length instructio ns (basic instructions) instruction execution spe ed: 1 instruction per cycle instructions including memory-t o-memory transfer, bit manip- ulation, and barrel shift instructions: instructions suitable for embedded applications function entry/exit instructions and register data multi-load store instructions : instructions supporting c language register interlock function: facilitating assembly-language coding built-in multiplier with instruction-level support signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles interrupts (save pc/ps): 6 cycles (16 priority levels) harvard architecture enabling program access and data access to be performed simultaneously instructions compatible with the fr family internal peripheral resources general-purpose ports: maximum 73 ports dmac (dma controller) maximum of 5 channels able to operate simultaneously. 2 transfer sources (internal peripheral/software) activation source can be selected using software. addressing mode specifies full 32-bit addresses (increment/decrement/fixed) transfer mode (demand transf er/burst transfer/step transfer/block transfer) transfer data size selectable from 8/16/32-bit multi-byte transfer enabled (by software) dmac descriptor in i/o areas (200 h to 240 h , 1000 h to 1024 h ) a/d converter (successive approximation type) 10-bit resolution: 26 channels conversion time: minimum 1 ? s external interrupt inputs: 10 channels shares the can rx pin and the i 2 c sda pin bit search module (for realos) function to search from the msb (most significant bit) for the position of the first ?0?, ?1 ?, or changed bit in a word lin-usart (full duplex double buffer): 5 channels clock synchronous/asynchronous selectable sync-break detection internal dedicated baud rate generator i 2 c bus interface (supports 400 kbps): 1 channel master/slave transmission and reception arbitration function, clock synchronisation function can controller (c-can): 1 channel maximum transfer speed: 1 mbps 32 transmission/reception message buffers 16-bit ppg timer: 12 channels 16-bit reload timer: 8 channels 16-bit free-run timer: 8 channels (1 channel each for icu and ocu) input capture: 8 channels (operat es in conjunction with the free-run timer) output compare: 8 channels (operates in conjunction with the free-run timer) watchdog timer real-time clock low-power consumption modes : sleep/stop mode function supply supervisor: low voltage detection circuit for external v dd 5 and internal 1.8v core voltage clock supervisor monitors the sub-clock (32 khz) and the main clock (4 mhz) ,
mb91460k series document number: 002-04602 rev. *a page 2 of 86 86 and switches to a recovery clock (cr oscillator, etc.) when the oscillations stop. clock modulator clock monitor sub-clock calibration corrects the real-time clock time r when operating with the 32 khz or cr oscillator main oscillator stabilisation timer generates an interrupt in sub-cl ock mode after the stabilisation wait time has elapsed on the 23-bit stabilisation wait time counter sub-oscillator stabilisation timer generates an interrupt in main clock mode after the stabili- sation wait time has elapsed on the 15-bit stabilisation wait time counter package and technology package: 120-pin plastic lqfp (lqfp-120) cmos 0.18 ? m technology power supply range 3 v to 5 v (1.8 v internal logic provided by a step-down voltage converter) operating temperature range: between ? 40c and ? 105c
mb91460k series document number: 002-04602 rev. *a page 3 of 86 86 contents 11. product lineup ............................................................. 4 2. pin assignment ............................................................ 6 2.1 mb91f465kx ................................................................. 6 3. pin description ............................................................. 7 3.1 mb91f465kx ................................................................. 7 3.2 power supply/ground pins.......................................... 10 4. i/o circuit types ......................................................... 11 5. handling devices ....................................................... 18 5.1 preventing latch-up..................................................... 18 5.2 handling of unused input pi ns .................................... 18 5.3 power supply pins....................................................... 18 5.4 crystal oscillator circuit............................................... 18 5.5 notes on using external clock..................................... 18 5.6 mode pins (md_x) ....................................................... 19 5.7 notes on operating in pll clock mode....................... 19 5.8 pull-up control............................................................. 19 5.9 notes on ps register .................................................. 19 6. notes on debugger .................................................... 20 6.1 execution of the reti command ................................ 20 6.2 break function............................................................. 20 6.3 operand break............................................................. 20 7. block diagram ............................................................ 21 7.1 mb91f465kx ............................................................... 21 8. cpu and control unit ................................................ 22 8.1 features....................................................................... 22 8.2 internal architecture..................................................... 22 8.3 programming model..................................................... 23 8.4 registers...................................................................... 24 9. embedded program/data memory (flash) ............... 27 9.1 flash features.............................................................. 27 9.2 operation modes .......................................................... 27 9.3 flash access in cpu mode .......................................... 28 9.4 parallel flash programming mode................................ 30 9.5 power on sequence in parallel programming mode .... 32 9.6 flash security ............................................................... 32 10. memory space ............................................................. 34 11. memory maps .............................................................. 35 11.1 mb91f465kx ................................................................ 35 12. i/o map ......................................................................... 36 12.1 mb91f465kx ................................................................ 36 12.2 flash memory and external bus area .......................... 53 13. interrupt vector table ................................................. 55 14. recommended settings ............................................. 60 14.1 pll and clockgear settings .... ............... .............. ......... 60 14.2 clock modulator settings...... ........................................ 61 15. electrical characteristics ........................................... 65 15.1 absolute maximum ratings............................................ 65 15.2 recommended operating condi tions........................... 67 15.3 dc characteristics ............. ........................................... 68 15.4 a/d converter characteristic s ...................................... 71 15.5 flash memory program/erase characteristics.............. 75 15.6 ac characteristics ........................................................ 76 16. ordering information .................................................. 82 17. package dimension .................................................... 83 18. main changes in this edition ..................................... 84 document history ................................................................85
mb91460k series document number: 002-04602 rev. *a page 4 of 86 86 1. product lineup feature mb91v460a (evaluation device) mb91f465ka mb91f465kb max. core frequency (clkb) 80mhz 80mhz max. resource frequency (clkp) 40mhz 40mhz max. external bus freq. (clkt) 40mhz 40mhz max. can frequency (clkcan) 20mhz 40mhz technology 0.35 ? m 0.18 ? m watchdog timer yes yes watchdog timer (rc osc. based) yes (disengageable) yes bit search yes yes reset input (initx) yes yes hardware standby input (hstx) yes - clock modulator yes yes low power mode yes yes dma 5 ch 5 ch mmu/mpu mpu (16 ch) [1] mpu (2 ch) [1] flash memory emulation sram 32bit read data 544 kbyte satellite flash memory n.a. - flash protection n.a. yes d-ram 64 kbyte 8 kbyte id-ram 64 kbyte 8 kbyte flash-cache (f-cache) 16 kbyte 4 kbyte boot-rom / bi-rom 4 kbyte fixed 4 kbyte rtc 1 ch 1 ch free running timer 8 ch 8 ch icu 8 ch 8 ch ocu 8 ch 8 ch reload timer 8 ch 8 ch ppg 16-bit 16 ch 12 ch pfm 16-bit 1 ch - sound generator 1 ch - up/down counter (8/16-bit) 4 ch (8-bit) / 2 ch (16-bit) - c_can 6 ch (128msg) 1 ch (32msg) lin-usart 4 ch + 4 ch fifo + 8 ch 4 ch + 1 ch fifo i2c (400k) 4 ch 1 ch
mb91460k series document number: 002-04602 rev. *a page 5 of 86 86 fr external bus yes (32bit addr, 32bit data) - external interrupts 16 ch 10 ch nmi interrupts 1 ch - smc 6 ch - lcd controller (40x4) 1 ch - adc (10 bit) 32 ch 26 ch alarm comparator 2 ch - supply supervisor (low voltage detection) yes yes clock supervisor yes yes main clock oscillator 4mhz 4mhz sub clock oscillator 32khz 32khz rc oscillator 100khz 100khz / 2mhz pll x 20 x 20 dsu4 yes - edsu yes (32 bp) [1] yes (4 bp) [1] supply voltage 3v / 5v 3v / 5v regulator yes yes power consumption n.a. < 900 mw temperature range (t a ) 0..70 c -40..105c package bga660 lqfp120 power on to pll run < 20 ms < 20 ms flash download time n.a. < 5 sec typical 1. mpu channels use edsu breakpoint registers (shared operation between mpu and edsu). feature mb91v460a (evaluation device) mb91f465ka mb91f465kb
mb91460k series document number: 002-04602 rev. *a page 6 of 86 86 2. pin assignment 2.1 mb91f465kx (top view) fpt-120p-m21 lqfp-120 vss5 monclk md_2 md_1 x0 x1 vss5 x1a x0a md_0 p16_1 / ppg9 p16_0 / ppg8 p20_7 p20_6 / sck3 / ck3 p20_5 / sot3 p20_4 / sin3 p20_3 p20_2 / sck2 / ck2 p20_1 / sot2 p20_0 / sin2 p16_5 p16_4 p24_7 / int7 p24_6 / int6 p24_5 / int5 p24_4 / int4 p24_3 / int3 p24_2 / int2 p24_1 / int1 vdd5 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 vdd5 1 90 vss5 p14_0 / icu0+tin0 / tin0 / ttg8/0 2 89 p24_0 / int0 p14_1 / icu1+tin1 / tin1 / ttg9/1 3 88 p22_1 / tx4 p14_2 / icu2+tin2 / tin2 / ttg10/2 4 87 p22_0 / rx4 / int12 p14_3 / icu3+tin3 / tin3 / ttg11/3 5 86 p15_3 / ocu3 / tot3 p14_4 / icu4+tin4 / tin4 / ttg4 6 85 p15_2 / ocu2 / tot2 p14_5 / icu5+tin5 / tin5 / ttg5 7 84 p15_1 / ocu1 / tot1 p14_6 / icu6+tin6 / tin6 / ttg6 8 83 p15_0 / ocu0 / tot0 p14_7 / icu7+tin7 / tin7 / ttg7 9 82 p16_3 / ppg11 p15_4 / ocu4 / tot4 10 81 p16_2 / ppg10 p15_5 / ocu5 / tot5 11 80 p17_7 / ppg7 p15_6 / ocu6 / tot6 12 79 p17_6 / ppg6 p15_7 / ocu7 / tot7 13 78 p17_5 / ppg5 p19_6 / frck5 14 77 vss5 vdd5r 15 76 vdd5 vcc18c 16 75 p21_7 vss5 17 74 p21_6 / sck1 / ck1 vdd5 18 73 p21_5 / sot1 p26_0 / an24 19 72 p21_4 / sin1 p26_1 / an25 20 71 p21_3 p27_0 / an16 21 70 p21_2 / sck0 / ck0 p27_1 / an17 22 69 p21_1 / sot0 p27_2 / an18 23 68 p21_0 / sin0 p27_3 / an19 24 67 p17_4 / ppg4 p27_4 / an20 25 66 p17_3 / ppg3 p27_5 / an21 26 65 p17_2 / ppg2 p27_6 / an22 27 64 p16_6 p27_7 / an23 28 63 p16_7 / atgx p28_0 / an8 29 62 initx vdd5 30 61 vss5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vss5 p28_1 / an9 p28_2 / an10 p28_3 / an11 p28_4 / an12 avcc5 avrh5 avss p29_0 / an0 p29_1 / an1 p29_2 / an2 p29_3 / an3 p29_4 / an4 p29_5 / an5 p29_6 / an6 p29_7 / an7 p28_5 / an13 vss5 p28_6 / an14 p28_7 / an15 p22_4 / sda0 / int14 p22_5 / scl0 p19_0 / sin4 p19_1 / sot4 p19_2 / sck4 / ck4 p18_2 / ck6 p18_6 / ck7 p17_0 / ppg0 p17_1 / ppg1 vdd5 qfp-120
mb91460k series document number: 002-04602 rev. *a page 7 of 86 86 3. pin description 3.1 mb91f465kx pin no. pin name i/o i/o circuit type [1] description 2 to 9 p14_0 to p14_7 i/o a general-purpose input/output ports icu0 to icu7 input capture input pins tin0 to tin7 external trigger input pins for reload timer ttg0/8 to ttg3/11, ttg4 to ttg7 external trigger input pins for ppg timer 10 to 13 p15_4 to p15_7 i/o a general-purpose input/output ports ocu4 to ocu7 output compare output pins tot4 to tot7 reload timer output pins 14 p19_6 i/o a general-purpose input/output port ck5 external clock input pin for free-run timer 5 19, 20 p26_0, p26_1 i/o b general-purpose input/output ports an24, an25 analog input pins for a/d converter 21 to 28 p27_0 to p27_7 i/o b general-purpose input/output ports an16 to an23 analog input pins for a/d converter 29, 32 to 35 p28_0 to p28_4 i/o b general-purpose input/output ports an8 to an12 analog input pins for a/d converter 39 to 46 p29_0 to p29_7 i/o b general-purpose input/output ports an0 to an7 analog input pins for a/d converter 47, 49, 50 p28_5 to p28_7 i/o b general-purpose input/output ports an13 to an15 analog input pins for a/d converter 51 p22_4 i/o c general-purpose input/output port sda0 i 2 c bus data input/output pin int14 external interrupt input pin 52 p22_5 i/o c general-purpose input/output port scl0 i 2 c bus clk input/output pin 53 p19_0 i/o a general-purpose input/output port sin4 data input pin for usart4 54 p19_1 i/o a general-purpose input/output port sot4 data output pin for usart4 55 p19_2 i/o a general-purpose input/output port sck4 clock input/output pin for usart4 ck4 external clock input pin for free-run timer 4 56, 57 p18_2, p18_6 i/o a general-purpose input/output port ck6, ck7 external clock input pin for free-run timers 6,7
mb91460k series document number: 002-04602 rev. *a page 8 of 86 86 58, 59 p17_0, p17_1 i/o a general-purpose input/output ports ppg0, ppg1 ppg timer output pins 62 initx i h external reset input pin 63 p16_7 i/o a general-purpose input/output port atgx a/d converter external trigger input pin 64 p16_6 i/o a general-purpose input/output port 65 to 67 p17_2 to p17_4 i/o a general-purpose input/output ports ppg2 to ppg4 ppg timer output pins 68 p21_0 i/o a general-purpose input/output port sin0 data input pin for usart0 69 p21_1 i/o a general-purpose input/output port sot0 data output pin for usart0 70 p21_2 i/o a general-purpose input/output port sck0 clock input/output pin for usart0 ck0 external clock input pin for free-run timer 0 71 p21_3 i/o a general-purpose input/output port 72 p21_4 i/o a general-purpose input/output port sin1 data input pin for usart1 73 p21_5 i/o a general-purpose input/output port sot1 data output pin for usart1 74 p21_6 i/o a general-purpose input/output port sck1 clock input/output pin for usart1 ck1 external clock input pin for free-run timer 1 75 p21_7 i/o a general-purpose input/output port 78 to 80 p17_5 to p17_7 i/o a general-purpose input/output ports ppg5 to ppg7 ppg timer output pins 81, 82 p16_2, p16_3 i/o a general-purpose input/output ports ppg10, ppg11 ppg timer output pins 83 to 86 p15_0 to p15_3 i/o a general-purpose input/output ports ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 87 p22_0 i/o a general-purpose input/output port rx4 rx input pin for can4 int12 external interrupt input pin 88 p22_1 i/o a general-purpose input/output port tx4 tx output pin for can4 89, 92 to 98 p24_0 to p24_7 i/o a general-purpose input/output ports int0 to int7 external interrupt input pins 99, 100 p16_4, p16_5 i/o a general-purpose input/output ports pin no. pin name i/o i/o circuit type [1] description
mb91460k series document number: 002-04602 rev. *a page 9 of 86 86 101 p20_0 i/o a general-purpose input/output port sin2 data input pin for usart2 102 p20_1 i/o a general-purpose input/output port sot2 data output pin for usart2 103 p20_2 i/o a general-purpose input/output port sck2 clock input/output pin for usart2 ck2 external clock input pin for free-run timer 2 104 p20_3 i/o a general-purpose input/output port 105 p20_4 i/o a general-purpose input/output port sin3 data input pin for usart3 106 p20_5 i/o a general-purpose input/output port sot3 data output pin for usart3 107 p20_6 i/o a general-purpose input/output port sck3 clock input/output pin for usart3 ck3 external clock input pin for free-run timer 3 108 p20_7 i/o a general-purpose input/output port 109, 110 p16_0, p16_1 i/o a general-purpose input/output ports ppg8, ppg9 ppg timer output pins 111 md_0 i g mode setting pin 112 x0a - j2 sub clock (oscillation) input 113 x1a - j2 sub clock (oscillation) output 115 x1 - j1 clock (oscillation) output 116 x0 - j1 clock (oscillation) input 117 md_1 i g mode setting pins 118 md_2 i g 119 monclk o m clock monitor pin 1. for information about the i/o circuit type, refer to ? i/o circuit types ?. pin no. pin name i/o i/o circuit type [1] description
mb91460k series document number: 002-04602 rev. *a page 10 of 86 86 3.2 power supply/ground pins pin no. pin name description 17, 31, 46, 61, 77, 90, 114, 120 vss5 ground pins 1, 18, 30, 60, 76, 91 vdd5 power supply pins 15 vdd5r power supply pin for internal regulator 38 avss5 analog ground pin for a/d converter 36 avcc5 power supply pin for a/d converter 37 avrh5 reference power supply pin for a/d converter 16 vcc18c capacitor connection pin for internal regulator
mb91460k series document number: 002-04602 rev. *a page 11 of 86 86 4. i/o circuit types type circuit remarks a cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown
mb91460k series document number: 002-04602 rev. *a page 12 of 86 86 b cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input c cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control data line standby control for input shutdown
mb91460k series document number: 002-04602 rev. *a page 13 of 86 86 d cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input e cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks r analog input pull-up control pull- down control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown
mb91460k series document number: 002-04602 rev. *a page 14 of 86 86 f cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input g mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin 12 v withstand (for md [2:0]) h cmos hysteresis input pin pull-up resistor value: 50 k ? approx. type circuit remarks r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown r hysteresis inputs r pull-up resistor hysteresis inputs
mb91460k series document number: 002-04602 rev. *a page 15 of 86 86 j1 high-speed oscillation circuit: programmable between oscillat ion mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (exter nal clock connected to x0 pin) feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode. j2 low-speed oscillation circuit: feedback resistor = approx. 2 * 5 m ? . feedback resistor is grounded in the center when the oscillator is disabled. type circuit remarks x1 x0 r r xout fci 0 1 fci or osc disable x1a x0a r r xout osc disable
mb91460k series document number: 002-04602 rev. *a page 16 of 86 86 k cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. lcd seg/com output type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown lcd seg/com
mb91460k series document number: 002-04602 rev. *a page 17 of 86 86 l cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input lcd voltage input m cmos level tri-state output(i ol = 5ma, i oh = -5ma) n analog input pin with protection type circuit remarks r pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown vlcd tri-state control data line analog input line
mb91460k series document number: 002-04602 rev. *a page 18 of 86 86 5. handling devices 5.1 preventing latch-up latch-up may occur in a cmos ic if a voltage higher than (v dd 5) or less than (v ss 5) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. if latch-up occurs, the power supply current increases rapidly, sometimes result ing in thermal breakdown of the device. therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. 5.2 handling of unused input pins if unused input pins are left open, abnormal operation may re sult. any unused input pins should be connected to pull-up or pull-down resistor (2k ? to 10k ? ) or enable internal pullup or pulldown resist ers (pper/ppcr) before t he input enable (porten) is activated by software. the mode pins md_x can be connected to v ss 5 or v dd 5 directly. unused alarm input pins can be connected to av ss 5 directly. 5.3 power supply pins in mb91460k series, devices including multiple power supply pi ns and ground pins are designed as follows; pins necessary to be at the same potential are interconnected in ternally to prevent malfunctions such as latch-up. all of the power supply pins a nd ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level risi ng and to follow the total output current ratings. furthermor e, the power supply pins and ground pins of the mb91460k series must be connected to the cu rrent supply source via a low impedance.it is also recommended to connect a ceramic capacitor of approximately 0.1 ? f as a bypass capacitor between power supply pin and ground pin near this device.this series has a built-in step-down regulator. connect a bypass capacitor of 4.7 ? f (use a x7r ceramic capacitor) to vcc18c pin for the regulator. 5.4 crystal oscillator circuit noise in proximity to the x0 (x0a) and x1 (x1a) pins can caus e the device to operate abnormally. printed circuit boards should be designed so that the x0 (x0a) and x1 (x 1a) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. it is recommended that the printed circui t board layout be designed such that the x0 and x1 pins or x0a and x1a pins are surrounded by ground plane for the stable operation. please request the oscillator manufacturer to evaluate the os cillational characteristics of the crystal and this device. 5.5 notes on using external clock when using the external clock, it is necessary to simultaneou sly supply the x0 (x0a) and the x1 (x1a) pins. in the described combination, x1 (x1a) should be supplied with a clock signal whic h has the opposite phase to the x0 (x0a) pins. at x0 and x1, a frequency up to 16 mhz is possible. example of using opposite phase supply x0 (x0a) x1 (x1a)
mb91460k series document number: 002-04602 rev. *a page 19 of 86 86 5.6 mode pins (md_x) these pins should be connected directly to the power supply or ground pins. to prevent the de vice from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance. 5.7 notes on operatin g in pll clock mode if the oscillator is disconnected or the clock input stops when the pll clock is selected, the microcontroller may continue to operate at the free-running frequency of th e self-oscillating circuit of the pll. howe ver, this self-running operation cannot be guaranteed. 5.8 pull-up control the ac standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin. 5.9 notes on ps register as the ps register is processed in advance by some instruct ions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the ps register being upd ated. as the microcontroller is designed to carry out reprocessing co rrectly upon returning from such an eit event,the operation befo re and after the eit always proceeds according to specification. the following behavior may occur if any of the following occurs in the instruction immediately after a div0u/div0s instruction: (a) a user interrupt or nmi is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. d0 and d1 flags are updated in advance. 2. an eit handling routine (user interru pt/nmi or emulator) is executed. 3. upon returning from the eit, the div0u/div0s instructio n is executed and the d0 and d1 flags are updated to the same values as those in 1. the following behavior o ccurs when an orccr, stilm, mov ri,ps instruction is executed to enable a user interrupt or nmi source while that interrupt is in the active state. 1. the ps register is updated in advance. 2. an eit handling routine (user interru pt/nmi or emulator) is executed. 3. upon returning from the eit, the abov e instructions are executed and the ps register is updated to the same value as in 1.
mb91460k series document number: 002-04602 rev. *a page 20 of 86 86 6. notes on debugger 6.1 execution of the reti command if single-step execution is used in an environment where an interrupt occurs freque ntly, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other pr ocessing. this will prevent the main routine and the handlers f or low priority level interrupts from being exec uted (for example, if the time-base timer interrupt is enabled, stepping over the reti instruction will always break on the first line of the time-base timer interrupt handler). disable the corresponding interrupts when the corres ponding interrupt handling routine no longer needs debugging. 6.2 break function i f the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execut ion will break after each instruction regardless of whether the us er program actually contains data access instructions. to prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks). 6.3 operand break it may cause malfunctions if a stack pointer exists in the area which is set as the dsu operand break. do not set the access to the areas containing the address of system sta ck pointer as a target of data event break.
mb91460k series document number: 002-04602 rev. *a page 21 of 86 86 7. block diagram 7.1 mb91f465kx p21_7, p21_3 p20_7, p20_3 ttg0/8 to ttg3/11, ttg4 to ttg7 ppg0 to ppg11 tin0 to tin7 tot0 to tot7 ck0 to ck7 icu0 to icu7 ocu0 to ocu7 sda0 scl0 an0 to an25 atgx sin0 to sin4 sot0 to sot4 sck0 to sck4 rx4 tx4 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core id-ram 8 kbytes bus converter d-ram 8 kbytes bit search can 1 channel 32 <-> 16 bus adapter clock modulator clock monitor monclk interrupt controller int0 to int7, int12, int14 external interrupt 10 channels clock supervisor clock control ppg timer 12 channels reload timer 8 channels free-run timer 8 channels input capture 8 channels output compare 8 channels general purpose io ports without resource, 7 pins lin-usart 5 channels 1 channel i c 2 real time clock a/d converter 26 channels dmac 5 channels p16_4 to p16_6 flash-cache 4 kbytes flash memory 544 kbytes
mb91460k series document number: 002-04602 rev. *a page 22 of 86 86 8. cpu and control unit the fr family cpu is a high performance co re that is designed based on the risc ar chitecture with advanced instructions for embedded applications. 8.1 features adoption of risc architecture basic instruction: 1 instruction per cycle general-purpose registers: 32-bit 16 registers 4 gbytes linear memory space multiplier installed 32-bit 32-bit multiplication: 5 cycles 16-bit 16-bit multiplication: 3 cycles enhanced interrupt processing function quick response speed (6 cycles) multiple-interrupt support level mask function (16 levels) enhanced instructions for i/o operation memory-to-memory tr ansfer instruction bit processing instruction basic instruction wo rd length: 16 bits low-power consumption sleep mode/stop mode 8.2 internal architecture the fr family cpu uses the harvard architecture in which the instruction bus and data bus are independent of each other. a 32-bit ? 16-bit buffer is connected to the 32-bit bus (d-bus ) to provide an interface between the cpu and peripheral resources. a harvard ? princeton bus converter is connected to both the i-bus and d-bus to provide an interface between the cpu and the bus controller.
mb91460k series document number: 002-04602 rev. *a page 23 of 86 86 8.3 programming model 8.3.1 basic programming model ilm scr ccr fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 pc rs rp tbr ssp usp mdl mdh . . . . . . 32 bits initial value general-purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiply & divide registers ps
mb91460k series document number: 002-04602 rev. *a page 24 of 86 86 8.4 registers 8.4.1 general-purpose register registers r0 to r15 are general-purpose registers. these regist ers can be used as accumulators for computation operations and a s pointers for memory access. of the 16 registers, enhanced commands are provided for the fo llowing registers to enable their use for particular applications . r13 : virtual accumulator r14 : frame pointer r15 : stack pointer initial values at reset are undefined for r0 to r14. the value for r15 is 00000000 h (ssp value). 8.4.2 ps (program status) this register holds the program status, and is divided into three parts, ilm, scr, and ccr. all undefined bits (-) in the diagram are reserved bits. the read values are always ? 0?. write access to these bits is invalid . fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 . . . . . . 32 bits initial value bit position bit 20 bit 0 bit 7 bit 8 bit 10 bit 16 ilm scr ccr bit 31
mb91460k series document number: 002-04602 rev. *a page 25 of 86 86 8.4.3 ccr (condition code register) sv: supervisor flag s: stack flag i: interrupt enable flag n: negative enable flag z: zero flag v: overflow flag c: carry flag 8.4.4 scr (system condition register) flag for step division (d1, d0) this flag stores interim data during execution of step division. step trace trap flag (t) this flag indicates whether the step trac e trap is enabled or disabled.the step trace trap function is used by emulators. when an emulator is in use, it cannot be used in execution of user programs. 8.4.5 ilm (interrupt level mask register) this register stores interrupt level mask values, and the values stored in ilm4 to ilm0 are used for level masking. the register is initialized to value ?01111 b ? at reset. 8.4.6 pc (program counter) the program counter indicates the address of the instruction that is being executed. the initial value at reset is undefined. - 000xxxx b bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 c v z n i s sv initial value bit 10 bit 8 bit 9 d1 d0 t xx0 b initial value bit 18 bit 16 bit 17 ilm2 ilm1 ilm0 01111 b ilm3 ilm4 bit 20 bit 19 initial value bit 0 bit 31 xxxxxxxx h initial value
mb91460k series document number: 002-04602 rev. *a page 26 of 86 86 8.4.7 tbr (table base register) the table base register stores the starting add ress of the vector tabl e used in eit processing. the initial value at reset is 000ffc00 h . 8.4.8 rp (return pointer) the return pointer stores the address for return from subroutines. during execution of a call instruction, the pc value is transferred to this rp register. during execution of a ret instruction, the conten ts of the rp register are transferred to pc. the initial value at reset is undefined. 8.4.9 usp (user stack pointer) the user stack pointer, when the s flag is ?1?, this register functions as the r15 register. the usp register can also be explicitly specified. the initial value at reset is undefined. this register cannot be used with reti instructions. 8.4.10 multiply & divide registers these registers are for multiplication and division, and are each 32 bits in length. the initial value at reset is undefined. bit 0 bit 31 000ffc00 h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 mdl bit 31 mdh
mb91460k series document number: 002-04602 rev. *a page 27 of 86 86 9. embedded program/data memory (flash) 9.1 flash features mb91f465kx: 544 kbytes (8 ?? 64 kbytes ? 4 ?? 8 kbytes) = 4.25 mbits programmable wait state for read/write access flash and boot security with security vector at 0x0014:8000 - 0x0014:800f boot security basic specification: same as mbm29lv400tc (e xcept size and part of sector configuration) 9.2 operation modes 9.2.1 32-bit cpu mode : cpu reads and executes programs in word (32-bit) length units. actual flash memory access is performed in word (32-bit) length units. 9.2.2 16-bit cpu mode : cpu reads and writes in half-word (16-bit) length units. program execution from the flash is not possible. actual flash memory access is performed in half-word (16-bit) length units. note : the operation mode of the flash memory can be selected usi ng a boot-rom function. the func tion start address is 0xbf60. the parameter description is given in the hardware manual in chapter 54.6 "flash access mode switching".
mb91460k series document number: 002-04602 rev. *a page 28 of 86 86 9.3 flash access in cpu mode 9.3.1 flash configuration 9.3.1.1 flash memory map mb91f465kx roms7 legend memory not available in this area addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h 000f:ffffh 000e:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) addr 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 memory available in this area addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1
mb91460k series document number: 002-04602 rev. *a page 29 of 86 86 9.3.2 flash access timing settings in cpu mode the following tables list all settings for a given maximum core fr equency (through the setting of clkb or maximum clock modulat ion) for flash read and write access. 9.3.2.1 flash read timing settings (synchronous read) 9.3.2.2 flash write timing settings (synchronous write) 9.3.3 address mapping from cpu to parallel programming mode the following tables show the calculation from cpu addres ses to flash macro addresses which are used in parallel programming. 9.3.3.1 address mapping mb91f465kx note : fa result is without 10:0000h offset for parallel flash programming . set offset by keeping fa[20] = 1 as described in sectio n ?parallel flash programming mode ?. core clock (clkb) atd aleh eq wexh wtc remark to 24 mhz 0 0 0 - 1 to 48 mhz 0 0 1 - 2 to 80 mhz 1 1 3 - 4 to 100 mhz 1 1 3 - 4 not available on mb91f465kx core clock (clkb) atd aleh eq wexh wtc remark to 32 mhz 1 - - 0 4 to 48 mhz 1 - - 0 5 to 64 mhz 1 - - 0 6 to 80 mhz 1 - - 0 7 to 100 mhz 1 - - 0 7 not available on mb91f465kx cpu address (addr) condition flash sectors fa (flash address) calculation 14:8000h to 14:ffffh addr[2]==0 sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 0d:0000h 14:8000h to 14:ffffh addr[2]==1 sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 0d:0000h + 00:2000h 08:0000h to 0f:ffffh addr[2]==0 sa12, sa14, sa16, sa18 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 00:0000h 08:0000h to 0f:ffffh addr[2]==1 sa13, sa15, sa17, sa19 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 - 00:0000h + 01:0000h
mb91460k series document number: 002-04602 rev. *a page 30 of 86 86 9.4 parallel flas h programming mode 9.4.1 flash configuration in pa rallel flash programming mode parallel flash programming mode (md[2:0] = 111): mb91f465kx sa0 (8kb) fa[1:0]=00 fa[1:0]=10 sa2 (8kb) sa1 (8kb) 0017:9fffh 0017:8000h sa4 (8kb) sa3 (8kb) 0017:dfffh 0017:c000h 0017:bfffh 0017:a000h sa6 (8kb) sa5 (8kb) 0017:ffffh 0017:e000h sa8 (64kb) sa7 (8kb) sa10 (64kb) sa9 (64kb) 0018:ffffh 0018:0000h sa12 (64kb) sa11 (64kb) 001a:ffffh 001a:0000h 0019:ffffh 0019:0000h sa14 (64kb) sa13 (64kb) 001c:ffffh 001c:0000h 001b:ffffh 001b:0000h sa16 (64kb) sa15 (64kb) 001e:ffffh 001e:0000h 001d:ffffh 001d:0000h sa17 (64kb) 001f:ffffh 001f:0000h sa19 (64kb) sa18 (64kb) dq[15:0] dq[15:0] remark: always keep fa[0] = 0 and fa[20] = 1 16bit write mode legend memory available in this area memory not available in this area fa[20:0]
mb91460k series document number: 002-04602 rev. *a page 31 of 86 86 9.4.2 pin connections in parallel programming mode resetting after setting the md[2:0] pins to [111] will halt cpu fu nctioning. at this time, the fl ash memory?s interface circuit enables direct control of the flash memory unit from external pins by directly linking some of the sig nals to general purpose ports. pl ease see table below for signal mapping. in this mode, the flash memory appears to t he external pins as a stand-alone unit. this mode is generally set when writing/eras ing using the parallel flash programmer. in this mode, all operations of the 8.5 mbits flash memory?s auto algorithms are available . table 1. correspondence between mbm29lv400tc and flash memory control signals mbm29lv400tc external pins fr-cpu mode mb91f465kx external pins comment flash memory mode normal function pin number - initx - initx 62 reset - frstx p16_7 63 -- md_2 md_2 118 set to ?1? -- md_1 md_1 117 set to ?1? -- md_0 md_0 111 set to ?1? ry/by fmcs:rdy bit ry/byx p24_0 89 byte internally fixed to ?h? bytex p24_2 93 we internal control signal + control via interface circuit wex p28_3 34 oe oex p28_2 33 ce cex p28_1 32 - atdin p22_1 88 set to ?0? - eqin p22_0 87 set to ?0? - testx p24_3 94 set to ?1? - rdyi p24_1 92 set to ?0? a-1 internal address bus fa0 p19_2 55 set to ?0? a0 to a7 fa1 to fa8 p27_0 to p27_7 21 to 28 a8 to a15 fa9 to fa16 p15_0 to p15_3, p15_4, p15_5 p21_0, p21_1 83 to 86, 10, 11, 68, 69 a16 to a18 fa17 to fa19 p21_2, p21_4, p21_5 70, 72, 73 - fa20,fa21 p21_6, p28_0 74, 29 set to ?1? dq0 to dq7 internal data bus dq0 to dq7 p17_0 to p17_7 58, 59, 65, 66, 67, 78, 79, 80 dq8 to dq15 dq8 to dq15 p14_0 to p14_7 2 to 9
mb91460k series document number: 002-04602 rev. *a page 32 of 86 86 9.5 power on sequence in parallel programming mode the flash memory can be accessed in programming mode after a ce rtain wait time, which is needed for security vector fetch: minimum wait time after vdd5/vdd5r power on: 2.76 ms minimum wait time afte r initx rising: 1.0 ms 9.6 flash security 9.6.1 vector addresses two flash security vectors (fsv1, fsv2) ar e located parallel to the boot security vectors (bsv1 , bsv2) controlling the protecti on functions of the flash security module: fsv1: 0x14:8000 bsv1: 0x14:8004 fsv2: 0x14:8008 bsv2: 0x14:800c 9.6.2 security vector fsv1 the setting of the flash security vector fsv1 is responsible fo r the read and write protection modes and the individual write p rotection of the 8 kbytes sectors. 9.6.2.1 fsv1 (bit31 to bit16) the setting of the flash security vector fsv1 bits [31: 16] is responsible for the read and write protection modes. table 2: explanation of the bits in the flash security vector fsv1 [31:16] fsv1[31:19] fsv1[18] write protection level fsv1[17] write protection fsv1[16] read protection flash security mode set all to ?0? set to ?0? set to ?0? set to ?1? read protection (all device modes, except intvec mode md[2:0] ? ?000?) set all to ?0? set to ?0? set to ?1? set to ?0? write protection (all device modes, without exception) set all to ?0? set to ?0? set to ?1? set to ?1? read protection (all device modes, except intvec mode md[2:0] ? ?000?) and write pro- tection (all device modes) set all to ?0? set to ?1? set to ?0? set to ?1? read protection (all device modes, except intvec mode md[2:0] ? ?000?) set all to ?0? set to ?1? set to ?1? set to ?0? write protection (all device modes, except intvec mode md[2:0] ? ?000?) set all to ?0? set to ?1? set to ?1? set to ?1? read protection (all device modes, except intvec mode md[2:0] ? ?000?) and write protection (all device modes except intvec mode md[2:0] ? ?000?)
mb91460k series document number: 002-04602 rev. *a page 33 of 86 86 9.6.2.2 fsv1 (bit15 to bit0) the setting of the flash security vector fsv1 bits [15:0] is responsible for the individual writ e protection of the 8 kbytes se ctors. it is only evaluated if write pr otection bit fsv1[17] is set. table 3: explanation of the bits in th e flash security vector fsv1 [15:0]: mb91f465kx : note: it is mandatory to always set the sector where the flash security vectors fsv1 and fsv2 are located to write protected (here sector sa4). otherwise it is possible to overwrite the security vector to a setting where it is possible to either read out the flash content or manipulate data by writing.see section ?flash access in cpu mode? for an overview about the sector organisation of t he flash memory. fsv1 bit sector enable write pro- tection disable write pro- tection comment fsv1[0] - set to ?0? set to ?1? not available fsv1[1] - set to ?0? set to ?1? not available fsv1[2] - set to ?0? set to ?1? not available fsv1[3] - set to ?0? set to ?1? not available fsv1[4] sa4 set to ?0? - write protection is mandatory! fsv1[5] sa5 set to ?0? set to ?1? fsv1[6] sa6 set to ?0? set to ?1? fsv1[7] sa7 set to ?0? set to ?1? fsv1[8] - set to ?0? set to ?1? not available fsv1[9] - set to ?0? set to ?1? not available fsv1[10] - set to ?0? set to ?1? not available fsv1[11] - set to ?0? set to ?1? not available fsv1[12] - set to ?0? set to ?1? not available fsv1[13] - set to ?0? set to ?1? not available fsv1[14] - set to ?0? set to ?1? not available fsv1[15] - set to ?0? set to ?1? not available
mb91460k series document number: 002-04602 rev. *a page 34 of 86 86 9.6.3 security vector fsv2 the setting of the flash security vector f sv2 bits [31:0] is responsible for the indi vidual write protection of the 64 kbytes s ectors. it is only evaluated if write protection bit fsv1 [17] is set. table 4: explanation of the bits in the flash security vector fsv2[31:0] mb91f465kx : note: see section ?flash access in cpu mode? for an overview about the sector organisation of the flash memory. 10. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing area the following address space area is used for i/o. this area is called direct addressing area, and the address of an operand can be specified directly in an instruction. the size of directly addressable area depends on the le ngth of the data being accessed as shown below. byte data access: 000 h to 0ff h half word access: 000 h to 1ff h word data access: 000 h to 3ff h fsv2 bit sector enable write pro- tection disable write protection comment fsv2[3:0] - set to ?0? set to ?1? not available fsv2[4] sa12 set to ?0? set to ?1? fsv2[5] sa13 set to ?0? set to ?1? fsv2[6] sa14 set to ?0? set to ?1? fsv2[7] sa15 set to ?0? set to ?1? fsv2[8] sa16 set to ?0? set to ?1? fsv2[9] sa17 set to ?0? set to ?1? fsv2[10] sa18 set to ?0? set to ?1? fsv2[11] sa19 set to ?0? set to ?1? fsv2[31:12] - set to ?0? set to ?1? not available
mb91460k series document number: 002-04602 rev. *a page 35 of 86 86 11. memory maps 11.1 mb91f465kx mb91f465kx 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00005000 h flash-cache (4 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002e000 h d-ram (0 wait, 8 kbytes) 00030000 h id-ram (8 kbytes) 00032000 h 00040000 h flash memory (512 kbytes) 00150000 h 00180000 h external bus area 00500000 h external data bus ffffffff h note: access prohibited areas 00148000 h flash memory (32 kbytes) 00100000 h external bus area external bus area 00080000 h
mb91460k series document number: 002-04602 rev. *a page 36 of 86 86 12. i/o map 12.1 mb91f465kx note: initial values of register bits are represented as follows: ? 1 ?: initial value ? 1 ? ? 0 ?: initial value ? 0 ? ? x ?: initial value ? undefined ? ? - ?: no physical regi ster at this location access is barred with an u ndefined data access attribute. address register block ? 0 ? 1 ? 2 ? 3 000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register read/write attribute register initial value after reset register name (column 1 register at address 4n, column 2 register at address 4n + 1...) leftmost register address (for word access, the register in column 1 becomes the msb side of the data.)
mb91460k series document number: 002-04602 rev. *a page 37 of 86 86 address register block ? 0 ? 1 ? 2 ? 3 000000 h to 000008 h reserved r-bus port data register 00000c h reserved pdr14 [r/w] xxxxxxxx pdr15 [r/w] xxxxxxxx 000010 h pdr16 [r/w] xxxxxxxx pdr17 [r/w] xxxxxxxx pdr18 [r/w] - x - - - x - pdr19 [r/w] - x - - - xxx 000014 h pdr20 [r/w] xxxx xxxx pdr21 [r/w] xxxx xxxx pdr22 [r/w] - - xx - - xx reserved 000018 h pdr24 [r/w] xxxxxxxx reserved pdr26 [r/w] - - - - - - xx pdr27 [r/w] xxxxxxxx 00001c h pdr28 [r/w] xxxxxxxx pdr29 [r/w] xxxxxxxx reserved 000020 h to 00002c h reserved reserved 000030 h eirr0 [r/w] xxxxxxxx enir0 [r/w] 00000000 elvr0 [r/w] 00000000 00000000 external interrupt (int0 to int7) 000034 h eirr1 [r/w] xxxxxxxx enir1 [r/w] 00000000 elvr1 [r/w] 00000000 00000000 external interrupt (int8 to int15) 000038 h dicr [r/w] - - - - - - - 0 hrcl [r/w] 0 - - 11111 reserved delay interrupt 00003c h reserved reserved 000040 h scr00 [r/w, w] 00000000 smr00 [r/w, w] 00000000 ssr00 [r/w, r] 00001000 rdr00/tdr00 [r/w] 00000000 lin-usart 0 000044 h escr00 [r/w] 00000x00 eccr00 [r/w, r, w] -00000xx reserved 000048 h scr01 [r/w, w] 00000000 smr01 [r/w, w] 00000000 ssr01 [r/w, r] 00001000 rdr01/tdr01 [r/w] 00000000 lin-usart 1 00004c h escr01 [r/w] 00000x00 eccr01 [r/w, r, w] -00000xx reserved 000050 h scr02 [r/w, w] 00000000 smr02 [r/w, w] 00000000 ssr02 [r/w, r] 00001000 rdr02/tdr02 [r/w] 00000000 lin-usart 2 000054 h escr02 [r/w] 00000x00 eccr02 [r/w, r, w] -00000xx reserved
mb91460k series document number: 002-04602 rev. *a page 38 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000058 h scr03 [r/w, w] 00000000 smr03 [r/w, w] 00000000 ssr03 [r/w, r] 00001000 rdr03/tdr03 [r/w] 00000000 lin-usart 3 00005c h escr03 [r/w] 00000x00 eccr03 [r/w, r, w] -00000xx reserved 000060 h scr04 [r/w, w] 00000000 smr04 [r/w, w] 00000000 ssr04 [r/w, r] 00001000 rdr04/tdr04 [r/w] 00000000 lin-usart 4 with fifo 000064 h escr04 [r/w] 00000x00 eccr04 [r/w, r, w] -00000xx fsr04 [r] - - - 00000 fcr04 [r/w] 0001 - 000 000068 h to 00007c h reserved reserved 000080 h bgr100 [r/w] 00000000 bgr000 [r/w] 00000000 bgr101 [r/w] 00000000 bgr001 [r/w] 00000000 baudrate generator lin-usart 0 to 4 000084 h bgr102 [r/w] 00000000 bgr002 [r/w] 00000000 bgr103 [r/w] 00000000 bgr003 [r/w] 00000000 000088 h bgr104 [r/w] 00000000 bgr004 [r/w] 00000000 reserved 00008c h to 0000cc h reserved reserved 0000d0 h ibcr0 [r/w] 00000000 ibsr0 [r] 00000000 itbah0 [r/w] - - - - - - 00 itbal0 [r/w] 00000000 i 2 c 0 0000d4 h itmkh0 [r/w] 00 - - - - 11 itmkl0 [r/w] 11111111 ismk0 [r/w] 01111111 isba0 [r/w] - 0000000 0000d8 h reserved idar0 [r/w] 00000000 iccr0 [r/w] 00011111 reserved 0000dc h to 0000fc h reserved reserved 000100 h gcn10 [r/w] 00110010 00010000 reserved gcn20 [r/w] - - - - 0000 ppg control 0 to 3 000104 h gcn11 [r/w] 00110010 00010000 reserved gcn21 [r/w] - - - - 0000 ppg control 4 to 7 000108 h gcn12 [r/w] 00110010 00010000 reserved gcn22 [r/w] - - - - 0000 ppg control 8 to 11 00010c h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 39 of 86 86 (continued) (continued) address register block ? 0 ? 1 ? 2 ? 3 000110 h ptmr00 [r] 11111111 11111111 pcsr00 [w] xxxxxxxx xxxxxxxx ppg 0 000114 h pdut00 [w] xxxxxxxx xxxxxxxx pcnh00 [r/w] 0000000 - pcnl00 [r/w] 000000 - 0 000118 h ptmr01 [r] 11111111 11111111 pcsr01 [w] xxxxxxxx xxxxxxxx ppg 1 00011c h pdut01 [w] xxxxxxxx xxxxxxxx pcnh01 [r/w] 0000000 - pcnl01 [r/w] 000000 - 0 000120 h ptmr02 [r] 11111111 11111111 pcsr02 [w] xxxxxxxx xxxxxxxx ppg 2 000124 h pdut02 [w] xxxxxxxx xxxxxxxx pcnh02 [r/w] 0000000 - pcnl02 [r/w] 000000 - 0 000128 h ptmr03 [r] 11111111 11111111 pcsr03 [w] xxxxxxxx xxxxxxxx ppg 3 00012c h pdut03 [w] xxxxxxxx xxxxxxxx pcnh03 [r/w] 0000000 - pcnl03 [r/w] 000000 - 0 000130 h ptmr04 [r] 11111111 11111111 pcsr04 [w] xxxxxxxx xxxxxxxx ppg 4 000134 h pdut04 [w] xxxxxxxx xxxxxxxx pcnh04 [r/w] 0000000 - pcnl04 [r/w] 000000 - 0 000138 h ptmr05 [r] 11111111 11111111 pcsr05 [w] xxxxxxxx xxxxxxxx ppg 5 00013c h pdut05 [w] xxxxxxxx xxxxxxxx pcnh05 [r/w] 0000000 - pcnl05 [r/w] 000000 - 0 000140 h ptmr06 [r] 11111111 11111111 pcsr06 [w] xxxxxxxx xxxxxxxx ppg 6 000144 h pdut06 [w] xxxxxxxx xxxxxxxx pcnh06 [r/w] 0000000 - pcnl06 [r/w] 000000 - 0 000148 h ptmr07 [r] 11111111 11111111 pcsr07 [w] xxxxxxxx xxxxxxxx ppg 7 00014c h pdut07 [w] xxxxxxxx xxxxxxxx pcnh07 [r/w] 0000000 - pcnl07 [r/w] 000000 - 0 000150 h ptmr08 [r] 11111111 11111111 pcsr08 [w] xxxxxxxx xxxxxxxx ppg 8 000154 h pdut08 [w] xxxxxxxx xxxxxxxx pcnh08 [r/w] 0000000 - pcnl08 [r/w] 000000 - 0 000158 h ptmr09 [r] 11111111 11111111 pcsr09 [w] xxxxxxxx xxxxxxxx ppg 9 00015c h pdut09 [w] xxxxxxxx xxxxxxxx pcnh09 [r/w] 0000000 - pcnl09 [r/w] 000000 - 0
mb91460k series document number: 002-04602 rev. *a page 40 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000160 h to 00017c h reserved reserved 000180 h reserved ics01 [r/w] 00000000 reserved ics23 [r/w] 00000000 input capture 0 to 3 000184 h ipcp0 [r] xxxxxxxx xxxxxxxx ipcp1 [r] xxxxxxxx xxxxxxxx 000188 h ipcp2 [r] xxxxxxxx xxxxxxxx ipcp3 [r] xxxxxxxx xxxxxxxx 00018c h ocs01 [r/w] - - - 0 - - 00 0000 - - 00 ocs23 [r/w] - - - 0 - - 00 0000 - - 00 output compare 0 to 3 000190 h occp0 [r/w] xxxxxxxx xxxxxxxx occp1 [r/w] xxxxxxxx xxxxxxxx 000194 h occp2 [r/w] xxxxxxxx xxxxxxxx occp3 [r/w] xxxxxxxx xxxxxxxx 000198 h , 00019c h reserved reserved 0001a0 h aderh [r/w] 00000000 00000000 aderl [r/w] 00000000 00000000 a/d converter 0001a4 h adcs1 [r/w] 00000000 adcs0 [r/w] 00000000 adcr1 [r] 000000xx adcr0 [r] xxxxxxxx 0001a8 h adct1 [r/w] 00010000 adct0 [r/w] 00101100 adsch [r/w] - - - 00000 adech [r/w] - - - 00000 0001ac h reserved reserved 0001b0 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 (ppg 0, ppg 1) 0001b4 h reserved tmcsrh0 [r/w] - - - 00000 tmcsrl0 [r/w] 0 - 000000 0001b8 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 (ppg 2, ppg 3) 0001bc h reserved tmcsrh1 [r/w] - - - 00000 tmcsrl1 [r/w] 0 - 000000 0001c0 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 (ppg 4, ppg 5) 0001c4 h reserved tmcsrh2 [r/w] - - - 00000 tmcsrl2 [r/w] 0 - 000000
mb91460k series document number: 002-04602 rev. *a page 41 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 0001c8 h tmrlr3 [w] xxxxxxxx xxxxxxxx tmr3 [r] xxxxxxxx xxxxxxxx reload timer 3 (ppg 6, ppg 7) 0001cc h reserved tmcsrh3 [r/w] - - - 00000 tmcsrl3 [r/w] 0 - 000000 0001d0 h tmrlr4 [w] xxxxxxxx xxxxxxxx tmr4 [r] xxxxxxxx xxxxxxxx reload timer 4 (ppg 8, ppg 9) 0001d4 h reserved tmcsrh4 [r/w] - - - 00000 tmcsrl4 [r/w] 0 - 000000 0001d8 h tmrlr5 [w] xxxxxxxx xxxxxxxx tmr5 [r] xxxxxxxx xxxxxxxx reload timer 5 (ppg 10, ppg 11) 0001dc h reserved tmcsrh5 [r/w] - - - 00000 tmcsrl5 [r/w] 0 - 000000 0001e0 h tmrlr6 [w] xxxxxxxx xxxxxxxx tmr6 [r] xxxxxxxx xxxxxxxx reload timer 6 (ppg 12, ppg 13) 0001e4 h reserved tmcsrh6 [r/w] - - - 00000 tmcsrl6 [r/w] 0 - 000000 0001e8 h tmrlr7 [w] xxxxxxxx xxxxxxxx tmr7 [r] xxxxxxxx xxxxxxxx reload timer 7 (ppg 14, ppg 15) (adc) 0001ec h reserved tmcsrh7 [r/w] - - - 00000 tmcsrl7 [r/w] 0 - 000000 0001f0 h tcdt0 [r/w] xxxxxxxx xxxxxxxx reserved tccs0 [r/w] 00000000 free running timer 0 (icu 0, icu 1) 0001f4 h tcdt1 [r/w] xxxxxxxx xxxxxxxx reserved tccs1 [r/w] 00000000 free running timer 1 (icu 2, icu 3) 0001f8 h tcdt2 [r/w] xxxxxxxx xxxxxxxx reserved tccs2 [r/w] 00000000 free running timer 2 (ocu 0, ocu1) 0001fc h tcdt3 [r/w] xxxxxxxx xxxxxxxx reserved tccs3 [r/w] 00000000 free running timer 3 (ocu 2, ocu3)
mb91460k series document number: 002-04602 rev. *a page 42 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h to 00023c h reserved 000240 h dmacr [r/w] 00 - - 0000 reserved 000244 h to 0002cc h reserved reserved 0002d0 h reserved ics045 [r/w] 00000000 reserved ics67 [r/w] 00000000 input capture 4 to 7 0002d4 h ipcp4 [r] xxxxxxxx xxxxxxxx ipcp5 [r] xxxxxxxx xxxxxxxx 0002d8 h ipcp6 [r] xxxxxxxx xxxxxxxx ipcp7 [r] xxxxxxxx xxxxxxxx 0002dc h ocs45 [r/w] - - - 0 - - 00 0000 - - 00 ocs67 [r/w] - - -0 - -00 0000 - -00 output compare 4 to 7 0002e0 h occp4 [r/w] xxxxxxxx xxxxxxxx occp5 [r/w] xxxxxxxx xxxxxxxx 0002e4 h occp6 [r/w] xxxxxxxx xxxxxxxx occp7 [r/w] xxxxxxxx xxxxxxxx 0002e8 h to 0002ec h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 43 of 86 86 0002f0 h tcdt4 [r/w] xxxxxxxx xxxxxxxx reserved tccs4 [r/w] 00000000 free running timer 4 (icu4, icu5) 0002f4 h tcdt5 [r/w] xxxxxxxx xxxxxxxx reserved tccs5 [r/w] 00000000 free running timer 5 (icu6, icu7) 0002f8 h tcdt6 [r/w] xxxxxxxx xxxxxxxx reserved tccs6 [r/w] 00000000 free running timer 6 (ocu4, ocu5) 0002fc h tcdt7 [r/w] xxxxxxxx xxxxxxxx reserved tccs7 [r/w] 00000000 free running timer 7 (ocu6, ocu7) 000300 h to 00038c h reserved reserved 000390 h roms [r] 11111111 01000011 reserved rom select register 000394 h to 0003ec h reserved reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h to 00043c h reserved reserved address register block ? 0 ? 1 ? 2 ? 3
mb91460k series document number: 002-04602 rev. *a page 44 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02 [r/w] ---11111 icr03 [r/w] ---11111 interrupt controller 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34 [r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 000470 h icr48 [r/w] ---11111 icr49 [r/w] ---11111 icr50 [r/w] ---11111 icr51 [r/w] ---11111 000474 h icr52 [r/w] ---11111 icr53 [r/w] ---11111 icr54 [r/w] ---11111 icr55 [r/w] ---11111 000478 h icr56 [r/w] ---11111 icr57 [r/w] ---11111 icr58 [r/w] ---11111 icr59 [r/w] ---11111 00047c h icr60 [r/w] ---11111 icr61 [r/w] ---11111 icr62 [r/w] ---11111 icr63 [r/w] ---11111 000480 h rsrr [r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] x0000x00 ctbr [w] xxxxxxxx clock control 000484 h clkr [r/w] 00000000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 45 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 00048c h plldivm [r/w] - - - 00000 plldivn [r/w] - - 000000 plldivg [r/w] - - - - 0000 pllmulg [w] 00000000 pll interface 000490 h pllctrl [r/w] - - - - 0000 reserved 000494 h oscc1 [r/w] - - - - - 010 oscs1 [r/w] 00001111 oscc2 [r/w] - - - - - 010 oscs2 [r/w] 00001111 main/sub oscillator control 000498 h porten [r/w] - - - - - - 00 reserved port input enable control 0004a0 h reserved wtcer [r/w] - - - - - - 00 wtcr [r/w] 00000000 000 - 00 - 0 real time clock (watch timer) 0004a4 h reserved wtbr [r/w] - - - xxxxx xxxxxxxx xxxxxxxx 0004a8 h wthr [r/w] - - - 00000 wtmr [r/w] - - 000000 wtsr [r/w] - - 000000 reserved 0004ac h csvtr [r/w] - - - 00010 csvcr [r/w] 00011100 cscfg [r/w] 0x000000 reserved clock supervisor / selector 0004b0 h cucr [r/w] - - - - - - - - - - - 0 - - 00 cutd [r/w] 10000000 00000000 calibration of sub clock 0004b4 h cutr1 [r] - - - - - - - - 00000000 cutr2 [r] 00000000 00000000 0004b8 h cmpr [r/w] - - 000010 11111101 reserved cmcr [r/w] - 001 - - 00 clock modulator 0004bc h cmt1 [r/w] 00000000 1 - - - 0000 cmt2 [r/w] - - 000000 - - 000000 0004c0 h canpre [r/w] 0 - - - 0000 canckd [r/w] - - - 0 - - - - reserved can clock control 0004c4 h lvsel [r/w] 00000111 lvdet [r/w] 0000 0 - 00 hwwde [r/w] - - - - - - 00 hwwd [r/w, w] 00011000 low voltage detection / hardware watchdog 0004c8 h oscrh [r/w] 000 - - 001 oscrl [r/w] - - - - - 000 wpcrh [r/w] 00 - - - 000 wpcrl [r/w] - - - - - - 00 main/sub oscillation stabilisation timer 0004cc h osccr [r/w] - - - - - - - 0 reserved regsel [r/w] - - 000110 regctr [r/w] - - - 0 - - 00 main oscillation standby control / main/sub regulator control 0004d0 h to 000d08 h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 46 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000d0c h reserved pdrd14 [r] xxxxxxxx pdrd15 [r] xxxxxxxx r-bus port data direct read register 000d10 h pdrd16 [r] xxxxxxxx pdrd17 [r] xxxxxxxx pdrd18 [r] - x - - - x - pdrd19 [r] - x - - - xxx 000d14 h pdrd20 [r] xxxx xxxx pdrd21 [r] xxxx xxxx pdrd22 [r] - - xx - - xx reserved 000d18 h pdrd24 [r] xxxxxxxx reserved pdrd26 [r] - - - - - - xx pdrd27 [r] xxxxxxxx 000d1c h pdrd28 [r] xxxxxxxx pdrd29 [r] xxxxxxxx reserved 000d20 h to 000d48 h reserved reserved 000d4c h reserved ddr14 [r/w] 00000000 ddr15 [r/w] 00000000 r-bus port direction register 000d50 h ddr16 [r/w] 00000000 ddr17 [r/w] 00000000 ddr18 [r/w] - 0 - - - 0 - ddr19 [r/w] - 0 - - - 000 000d54 h ddr20 [r/w] 0000 0000 ddr21 [r/w] 0000 0000 ddr22 [r/w] - - 00 - - 00 reserved 000d58 h ddr24 [r/w] 00000000 reserved ddr26 [r/w] - - - - - - 00 ddr27 [r/w] 00000000 000d5c h ddr28 [r/w] 00000000 ddr29 [r/w] 00000000 reserved 000d60 h to 000d88 h reserved reserved 000d8c h reserved pfr14 [r/w] 00000000 pfr15 [r/w] 00000000 r-bus port function register 000d90 h pfr16 [r/w] 0 - - - 0000 pfr17 [r/w] 00000000 pfr18 [r/w] - 0 - - - 0 - pfr19 [r/w] - 0 - - - 000 000d94 h pfr20 [r/w] - 000 - 000 pfr21 [r/w] - 000 - 000 pfr22 [r/w] - - 00 - - 00 reserved 000d98 h pfr24 [r/w] 00000000 reserved pfr26 [r/w] - - - - - - 00 pfr27 [r/w] 00000000 000d9c h pfr28 [r/w] 00000000 pfr29 [r/w] 00000000 reserved 000da0 h to 000dc8 h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 47 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000dcc h reserved epfr14 [r/w] 00000000 epfr15 [r/w] 00000000 r-bus expansion port function register 000dd0 h epfr16 [r/w] 0 - - - - - - - epfr17 [r/w] - - - - - - - - epfr18 [r/w] - 0 - - - - 0 - epfr19 [r/w] - 0 - - - 0 - - 000dd4 h epfr20 [r/w] - 0 - - - 0 - - epfr21 [r/w] - 0 - - - 0 - - epfr22 [r/w] - - - - - - - - reserved 000dd8 h epfr24 [r/w] - - - - - - - - reserved epfr26 [r/w] - - - - - - 00 epfr27 [r/w] 00000000 000ddc h epfr28 [r/w] - - - - - - - - epfr29 [r/w] - - - - - - - - reserved 000de0 h to 000e08 h reserved reserved 000e0c h reserved podr14 [r/w] 00000000 podr15 [r/w] 00000000 r-bus port output drive select register 000e10 h podr16 [r/w] 00000000 podr17 [r/w] 00000000 podr18 [r/w] - 0 - - - 0 - podr19 [r/w] - 0 - - - 000 000e14 h podr20 [r/w] 0000 0000 podr21 [r/w] 0000 0000 podr22 [r/w] - - 00 - - 00 reserved 000e18 h podr24 [r/w] 00000000 reserved podr26 [r/w] - - - - - - 00 podr27 [r/w] 00000000 000e1c h podr28 [r/w] 00000000 podr29 [r/w] 00000000 reserved 000e20 h to 000e48 h reserved reserved 000e4c h reserved pilr14 [r/w] 00000000 pilr15 [r/w] 00000000 r-bus pin input level select register 000e50 h pilr16 [r/w] 00000000 pilr17 [r/w] 00000000 pilr18 [r/w] - 0 - - - 0 - pilr19 [r/w] - 0 - - - 000 000e54 h pilr20 [r/w] 0000 0000 pilr21 [r/w] 0000 0000 pilr22 [r/w] - - 00 - - 00 reserved 000e58 h pilr24 [r/w] 00000000 reserved pilr26 [r/w] - - - - - - 00 pilr27 [r/w] 00000000 000e5c h pilr28 [r/w] 00000000 pilr29 [r/w] 00000000 reserved 000e60 h to 000e88 h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 48 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 000e8c h reserved epilr14 [r/w] 00000000 epilr15 [r/w] 00000000 r-bus expansion port input level select register 000e90 h epilr16 [r/w] 00000000 epilr17 [r/w] 00000000 epilr18 [r/w] - 0 - - - 0 - epilr19 [r/w] - 0 - - - 000 000e94 h epilr20 [r/w] 0000 0000 epilr21 [r/w] 0000 0000 epilr22 [r/w] - - 00 - - 00 reserved 000e98 h epilr24 [r/w] 00000000 reserved epilr26 [r/w] - - - - - - 00 epilr27 [r/w] 00000000 000e9c h epilr28 [r/w] 00000000 epilr29 [r/w] 00000000 reserved 000ea0 h to 000ec8 h reserved reserved 000ecc h reserved pper14 [r/w] 00000000 pper15 [r/w] 00000000 r-bus port pull-up/down enable register 000ed0 h pper16 [r/w] 00000000 pper17 [r/w] 00000000 pper18 [r/w] - 0 - - - 0 - pper19 [r/w] - 0 - - - 000 000ed4 h pper20 [r/w] 0000 0000 pper21 [r/w] 0000 0000 pper22 [r/w] - - 00 - - 00 reserved 000ed8 h pper24 [r/w] 00000000 reserved pper26 [r/w] - - - - - - 00 pper27 [r/w] 00000000 000edc h pper28 [r/w] 00000000 pper29 [r/w] 00000000 reserved 000ee0 h to 000f08 h reserved reserved 000f0c h reserved ppcr14 [r/w] 00000000 ppcr15 [r/w] 00000000 r-bus port pull-up/down control register 000f10 h ppcr16 [r/w] 00000000 ppcr17 [r/w] 00000000 ppcr18 [r/w] - 0 - - - 0 - ppcr19 [r/w] - 0 - - - 000 000f14 h ppcr20 [r/w] 0000 0000 ppcr21 [r/w] 0000 0000 ppcr22 [r/w] - - 00 - - 00 reserved 000f18 h ppcr24 [r/w] 00000000 reserved ppcr26 [r/w] - - - - - - 00 ppcr27 [r/w] 00000000 000f1c h ppcr28 [r/w] 00000000 ppcr29 [r/w] 00000000 reserved 000f20 h to 000f3c h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 49 of 86 86 (continued) address register block ? 0 ? 1 ? 2 ? 3 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 004ffc h reserved reserved 005000 h to 005ffc h mb91f465kx instruction ram/flash cache size is 4kb instruction ram / flash cache 006000 h to 006ffc h reserved reserved 007000 h fmcs [r/w] 01101000 fmcr [r] - - - 00000 fchcr [r/w] - - - - - - 00 10000011 flash memory/f-cache/ i-ram control register 007004 h fmwt [r/w] 11111111 11111111 fmwt2 [r] - 001 - - - - fmps [r/w] - - - - - 000 007008 h fmac [r] 00000000 00000000 00000000 00000000 00700c h fcha0 [r/w] - - - - - - - - - - - 00000 00000000 00000000 flash-cache non- cacheable area setting register 007010 h fcha1 [r/w] - - - - - - - - - - - 00000 00000000 00000000
mb91460k series document number: 002-04602 rev. *a page 50 of 86 86 (continued) (continued) address register block ? 0 ? 1 ? 2 ? 3 007014 h to 007ffc h reserved reserved 008000 h to 00bffc h mb91f465kx boot-rom size is 4 kbytes : 00b000 h to 00bffc h (instruction access is 1 wait cycle, data access is 1 wait cycle) boot rom area 00c000 h to 00c3fc h reserved reserved 00c400 h ctrlr4 [r/w] 00000000 00000001 statr4 [r/w] 00000000 00000000 can 4 control register 00c404 h errcnt4 [r] 00000000 00000000 btr4 [r/w] 00100011 00000001 00c408 h intr4 [r] 00000000 00000000 testr4 [r/w] 00000000 x0000000 00c40c h brpe4 [r/w] 00000000 00000000 reserved 00c410 h if1creq4 [r/w] 00000000 00000001 if1cmsk4 [r/w] 00000000 00000000 can 4 if 1 register 00c414 h if1msk24 [r/w] 11111111 11111111 if1msk14 [r/w] 11111111 11111111 00c418 h if1arb24 [r/w] 00000000 00000000 if1arb14 [r/w] 00000000 00000000 00c41c h if1mctr4 [r/w] 00000000 00000000 reserved 00c420 h if1dta14 [r/w] 00000000 00000000 if1dta24 [r/w] 00000000 00000000 00c424 h if1dtb14 [r/w] 00000000 00000000 if1dtb24 [r/w] 00000000 00000000 00c428 h to 00c42c h reserved 00c430 h if1dta24 [r/w] 00000000 00000000 if1dta14 [r/w] 00000000 00000000 00c434 h if1dtb24 [r/w] 00000000 00000000 if1dtb14 [r/w] 00000000 00000000 00c438 h , 00c43c h reserved
mb91460k series document number: 002-04602 rev. *a page 51 of 86 86 address register block ? 0 ? 1 ? 2 ? 3 00c440 h if2creq4 [r/w] 00000000 00000001 if2cmsk4 [r/w] 00000000 00000000 can 4 if 2 register 00c444 h if2msk24 [r/w] 11111111 11111111 if2msk14 [r/w] 11111111 11111111 00c448 h if2arb24 [r/w] 00000000 00000000 if2arb14 [r/w] 00000000 00000000 00c44c h if2mctr4 [r/w] 00000000 00000000 reserved 00c450 h if2dta14 [r/w] 00000000 00000000 if2dta24 [r/w] 00000000 00000000 00c454 h if2dtb14 [r/w] 00000000 00000000 if2dtb24 [r/w] 00000000 00000000 00c458 h , 00c45c h reserved 00c460 h if2dta24 [r/w] 00000000 00000000 if2dta14 [r/w] 00000000 00000000 00c464 h if2dtb24 [r/w] 00000000 00000000 if2dtb14 [r/w] 00000000 00000000 00c468 h to 00c47c h reserved 00c480 h treqr24 [r] 00000000 00000000 treqr14 [r] 00000000 00000000 can 4 status flags 00c484 h to 00c48c h reserved 00c490 h newdt24 [r] 00000000 00000000 newdt14 [r] 00000000 00000000 00c494 h to 00c49c h reserved 00c4a0 h intpnd24 [r] 00000000 00000000 intpnd14 [r] 00000000 00000000 00c4a4 h to 00c4ac h reserved 00c4b0 h msgval24 [r] 00000000 00000000 msgval14 [r] 00000000 00000000 00c4b4 h to 00effc h reserved reserved
mb91460k series document number: 002-04602 rev. *a page 52 of 86 86 (continued) 1. depends on the number of available can channels 2. acr0 [11 : 10] depends on bus width setting in mode vector fetch information 3. tcr [3 : 0] init value ? 0000, keeps value after rst address register block ? 0 ? 1 ? 2 ? 3 020000 h to 02fffc h mb91f465kx d-ram size is 8 kbytes : 02e000 h to 02fffc h (data access is 0 wait cycles) d-ram area 030000 h to 03fffc h mb91f465kx id-ram size is 8 kbytes : 030000 h to 031ffc h (instruction access is 0 wait cy cles, data access is 1 wait cycle) id-ram area
mb91460k series document number: 002-04602 rev. *a page 53 of 86 86 12.2 flash memory and external bus area 12.2.1 mb91f465kx 32bit read mode dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 040000 h to 05fff8 h reserved reserved roms0 060000 h to 07fff8 h reserved reserved roms1 080000 h to 09fff8 h sa12 (64kb) sa13 (64kb) roms2 0a0000 h to 0bfff8 h sa14 (64kb) sa15 (64kb) roms3 0c0000 h to 0dfff8 h sa16 (64kb) sa17 (64kb) roms4 0e0000 h to 0ffff0 h sa18 (64kb) fmv [r] 06 00 00 00 h sa19 (64kb) frv [r] 00 00 bf f8 h roms5 0ffff8 h 100000 h to 11fff8 h reserved reserved roms6 120000 h to 13fff8 h reserved reserved 140000 h to 143ff8 h reserved reserved roms7 144000 h to 17ff8 h reserved reserved 148000 h to 14bff8 h sa4 (8kb) sa5 (8kb) 14c000 h to 14fff8 h sa6 (8kb) sa7 (8kb) 150000 h to 17fff8 h reserved
mb91460k series document number: 002-04602 rev. *a page 54 of 86 86 note : write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the values shown above will be read. 180000 h to 1bfff8 h reserved roms8 1c0000 h to 1ffff8 h roms9 200000 h to 27fff8 h roms10 280000 h to 2ffff8 h roms11 300000 h to 37fff8 h roms12 380000 h to 3ffff8 h roms13 400000 h to 47fff8 h roms14 480000 h to 4ffff8 h roms15 32bit read mode dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7
mb91460k series document number: 002-04602 rev. *a page 55 of 86 86 13. interrupt vector table interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number deci- mal hexa-de cimal setting register register address offset default vector address reset 0 00 - - 3fc h 000ffffc h - mode vector 1 01 - - 3f8 h 000ffff8 h - system reserved 2 02 - - 3f4 h 000ffff4 h - system reserved 3 03 - - 3f0 h 000ffff0 h - system reserved 4 04 - - 3ec h 000fffec h - cpu supervisor mode (int #5 instruction) [5] 5 05 - - 3e8 h 000fffe8 h - memory protection exception [5] 6 06 - - 3e4 h 000fffe4 h - system reserved 7 07 - - 3e0 h 000fffe0 h - system reserved 8 08 - - 3dc h 000fffdc h - system reserved 9 09 - - 3d8 h 000fffd8 h - system reserved 10 0a - - 3d4 h 000fffd4 h - system reserved 11 0b - - 3d0 h 000fffd0 h - system reserved 12 0c - - 3cc h 000fffcc h - system reserved 13 0d - - 3c8 h 000fffc8 h - undefined instruction exception 14 0e - - 3c4 h 000fffc4 h - nmi request 15 0f f h fixed 3c0 h 000fffc0 h - external interrupt 0 16 10 icr00 440 h 3bc h 000fffbc h 0, 16 external interrupt 1 17 11 3b8 h 000fffb8 h 1, 17 external interrupt 2 18 12 icr01 441 h 3b4 h 000fffb4 h 2, 18 external interrupt 3 19 13 3b0 h 000fffb0 h 3, 19 external interrupt 4 20 14 icr02 442 h 3ac h 000fffac h 20 external interrupt 5 21 15 3a8 h 000fffa8 h 21 external interrupt 6 22 16 icr03 443 h 3a4 h 000fffa4 h 22 external interrupt 7 23 17 3a0 h 000fffa0 h 23 reserved 24 18 icr04 444 h 39c h 000fff9c h - reserved 25 19 398 h 000fff98 h - reserved 26 1a icr05 445 h 394 h 000fff94 h - reserved 27 1b 390 h 000fff90 h - external interrupt 12 28 1c icr06 446 h 38c h 000fff8c h - reserved 29 1d 388 h 000fff88 h - external interrupt 14 30 1e icr07 447 h 384 h 000fff84 h - reserved 31 1f 380 h 000fff80 h -
mb91460k series document number: 002-04602 rev. *a page 56 of 86 86 interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number deci- mal hexa-de cimal setting register register address offset default vector address reload timer 0 32 20 icr08 448 h 37c h 000fff7c h 4, 32 reload timer 1 33 21 378 h 000fff78 h 5, 33 reload timer 2 34 22 icr09 449 h 374 h 000fff74 h 34 reload timer 3 35 23 370 h 000fff70 h 35 reload timer 4 36 24 icr10 44a h 36c h 000fff6c h 36 reload timer 5 37 25 368 h 000fff68 h 37 reload timer 6 38 26 icr11 44b h 364 h 000fff64 h 38 reload timer 7 39 27 360 h 000fff60 h 39 free run timer 0 40 28 icr12 44c h 35c h 000fff5c h 40 free run timer 1 41 29 358 h 000fff58 h 41 free run timer 2 42 2a icr13 44d h 354 h 000fff54 h 42 free run timer 3 43 2b 350 h 000fff50 h 43 free run timer 4 44 2c icr14 44e h 34c h 000fff4c h 44 free run timer 5 45 2d 348 h 000fff48 h 45 free run timer 6 46 2e icr15 44f h 344 h 000fff44 h 46 free run timer 7 47 2f 340 h 000fff40 h 47 reserved 48 30 icr16 450 h 33c h 000fff3c h - reserved 49 31 338 h 000fff38 h - reserved 50 32 icr17 451 h 334 h 000fff34 h - reserved 51 33 330 h 000fff30 h - can 4 52 34 icr18 452 h 32c h 000fff2c h - reserved 53 35 328 h 000fff28 h - lin-usart 0 rx 54 36 icr19 453 h 324 h 000fff24 h 6, 48 lin-usart 0 tx 55 37 320 h 000fff20 h 7, 49 lin-usart 1 rx 56 38 icr20 454 h 31c h 000fff1c h 8, 50 lin-usart 1 tx 57 39 318 h 000fff18 h 9, 51 lin-usart 2 rx 58 3a icr21 455 h 314 h 000fff14 h 52 lin-usart 2 tx 59 3b 310 h 000fff10 h 53 lin-usart 3 rx 60 3c icr22 456 h 30c h 000fff0c h 54 lin-usart 3 tx 61 3d 308 h 000fff08 h 55 system reserved 62 3e icr23 [3] 457 h 304 h 000fff04 h - delayed interrupt 63 3f 300 h 000fff00 h -
mb91460k series document number: 002-04602 rev. *a page 57 of 86 86 interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number deci- mal hexa-de cimal setting register register address offset default vector address system reserved [4] 64 40 (icr24) (458 h ) 2fc h 000ffefc h - system reserved [4] 65 41 2f8 h 000ffef8 h - lin-usart (fifo) 4 rx 66 42 icr25 459 h 2f4 h 000ffef4 h 10, 56 lin-usart (fifo) 4 tx 67 43 2f0 h 000ffef0 h 11, 57 reserved 68 44 icr26 45a h 2ec h 000ffeec h 12, 58 reserved 69 45 2e8 h 000ffee8 h 13, 59 reserved 70 46 icr27 45b h 2e4 h 000ffee4 h 60 reserved 71 47 2e0 h 000ffee0 h 61 reserved 72 48 icr28 45c h 2dc h 000ffedc h 62 reserved 73 49 2d8 h 000ffed8 h 63 i 2 c 0 74 4a icr29 45d h 2d4 h 000ffed4 h - reserved 75 4b 2d0 h 000ffed0 h - reserved 76 4c icr30 45e h 2cc h 000ffecc h 64 reserved 77 4d 2c8 h 000ffec8 h 65 reserved 78 4e icr31 45f h 2c4 h 000ffec4 h 66 reserved 79 4f 2c0 h 000ffec0 h 67 reserved 80 50 icr32 460 h 2bc h 000ffebc h 68 reserved 81 51 2b8 h 000ffeb8 h 69 reserved 82 52 icr33 461 h 2b4 h 000ffeb4 h 70 reserved 83 53 2b0 h 000ffeb0 h 71 reserved 84 54 icr34 462 h 2ac h 000ffeac h 72 reserved 85 55 2a8 h 000ffea8 h 73 reserved 86 56 icr35 463 h 2a4 h 000ffea4 h 74 reserved 87 57 2a0 h 000ffea0 h 75 reserved 88 58 icr36 464 h 29c h 000ffe9c h 76 reserved 89 59 298 h 000ffe98 h 77 reserved 90 5a icr37 465 h 294 h 000ffe94 h 78 reserved 91 5b 290 h 000ffe90 h 79 input capture 0 92 5c icr38 466 h 28c h 000ffe8c h 80 input capture 1 93 5d 288 h 000ffe88 h 81 input capture 2 94 5e icr39 467 h 284 h 000ffe84 h 82 input capture 3 95 5f 280 h 000ffe80 h 83
mb91460k series document number: 002-04602 rev. *a page 58 of 86 86 interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number deci- mal hexa-de cimal setting register register address offset default vector address input capture 4 96 60 icr40 468 h 27c h 000ffe7c h 84 input capture 5 97 61 278 h 000ffe78 h 85 input capture 6 98 62 icr41 469 h 274 h 000ffe74 h 86 input capture 7 99 63 270 h 000ffe70 h 87 output compare 0 100 64 icr42 46a h 26c h 000ffe6c h 88 output compare 1 101 65 268 h 000ffe68 h 89 output compare 2 102 66 icr43 46b h 264 h 000ffe64 h 90 output compare 3 103 67 260 h 000ffe60 h 91 output compare 4 104 68 icr44 46c h 25c h 000ffe5c h 92 output compare 5 105 69 258 h 000ffe58 h 93 output compare 6 106 6a icr45 46d h 254 h 000ffe54 h 94 output compare 7 107 6b 250 h 000ffe50 h 95 reserved 108 6c icr46 46e h 24c h 000ffe4c h - reserved 109 6d 248 h 000ffe48 h - system reserved 110 6e icr47 [3] 46f h 244 h 000ffe44 h - system reserved 111 6f 240 h 000ffe40 h - ppg0 112 70 icr48 470 h 23c h 000ffe3c h 15, 96 ppg1 113 71 238 h 000ffe38 h 97 ppg2 114 72 icr49 471 h 234 h 000ffe34 h 98 ppg3 115 73 230 h 000ffe30 h 99 ppg4 116 74 icr50 472 h 22c h 000ffe2c h 100 ppg5 117 75 228 h 000ffe28 h 101 ppg6 118 76 icr51 473 h 224 h 000ffe24 h 102 ppg7 119 77 220 h 000ffe20 h 103 ppg8 120 78 icr52 474 h 21c h 000ffe1c h 104 ppg9 121 79 218 h 000ffe18 h 105 ppg10 122 7a icr53 475 h 214 h 000ffe14 h 106 ppg11 123 7b 210 h 000ffe10 h 107 reserved 124 7c icr54 476 h 20c h 000ffe0c h 108 reserved 125 7d 208 h 000ffe08 h 109 reserved 126 7e icr55 477 h 204 h 000ffe04 h 110 reserved 127 7f 200 h 000ffe00 h 111
mb91460k series document number: 002-04602 rev. *a page 59 of 86 86 3. icr23 and icr47 can be exchanged by setting the realos compatibility bit (addr 0c03 h : ios[0]) 4. used by realos 5. memory protection unit (mpu) support interrupt interrupt number interrupt level [1] 1. the interrupt control registers (icrs) are located in the inte rrupt controller and set the interrupt level for each interrupt request. an icr is provided for each interrupt request. interrupt vector [2] 2. the vector address for each eit (exception, interrupt or trap ) is calculated by adding the listed offset to the table base re gister value (tbr) . the tbr specifies the top of the eit vector table. the addresses listed in the table are for the default tbr value (000ffc00 h ) . the tbr is initialized to this value by a reset. the tbr is set to 000ffc00 h after the internal boot rom is executed. dma resource number decimal hexa-de cimal setting register register address offset default vector address reserved 128 80 icr56 478 h 1fc h 000ffdfc h - reserved 129 81 1f8 h 000ffdf8 h - reserved 130 82 icr57 479 h 1f4 h 000ffdf4 h - reserved 131 83 1f0 h 000ffdf0 h - real time clock 132 84 icr58 47a h 1ec h 000ffdec h - calibration unit 133 85 1e8 h 000ffde8 h - a/d converter 0 134 86 icr59 47b h 1e4 h 000ffde4 h 14, 112 reserved 135 87 1e0 h 000ffde0 h - reserved 136 88 icr60 47c h 1dc h 000ffddc h - reserved 137 89 1d8 h 000ffdd8 h - low voltage detection 138 8a icr61 47d h 1d4 h 000ffdd4 h - reserved 139 8b 1d0 h 000ffdd0 h - timebase overflow 140 8c icr62 47e h 1cc h 000ffdcc h - pll clock gear 141 8d 1c8 h 000ffdc8 h - dma controller 142 8e icr63 47f h 1c4 h 000ffdc4 h - main/sub osc stability wait 143 8f 1c0 h 000ffdc0 h - security vector 144 90 -- 1bc h 000ffdbc h - used by the int instruction. 145 to 255 91 to ff -- 1b8 h to 000 h 000ffdb8 h to 000ffc00 h -
mb91460k series document number: 002-04602 rev. *a page 60 of 86 86 14. recommended settings 14.1 pll and clockgear settings please note that for mb91f465kx, the core base clock frequencies are valid in the 1. 8v operation mode of the main regulator and flash. table 5: recommended pll divider and clockgear settings pll input (clk) [mhz] frequency parameter clockgear parameter pll output (x) [mhz] core base clock [mhz] remarks divm divn divg mulg mulg 4 2 25 16 24 200 100 [1] 1. this setting is not possible at mb91f465kx 4 2 24 16 24 192 96 [1] 4 2 23 16 24 184 92 [1] 4 2 22 16 24 176 88 [1] 4 2 21 16 20 168 84 [1] 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12
mb91460k series document number: 002-04602 rev. *a page 61 of 86 86 14.2 clock modulator settings the following table shows all possible settings for the clock mo dulator in a base clock frequency range from 32mhz up to 48mhz. base clock frequencies above 48 mhz are not allowed on mb91f465kx. the flash access time settings need to be adjusted according to fmax while the pll and clockgear settings should be set accordi ng to base clock frequency . table 6: clock modulator settings, frequency range and supported supply voltage modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] remarks 1 3 026f 48 44.2 52.5 1 5 02ae 48 41.8 56.4 1 7 02ed 48 39.6 60.9 1 9 032c 48 37.7 66.1 1 11 036b 48 35.9 72.3 1 13 03aa 48 34.3 79.9 1 15 03e9 48 32.8 89.1 [1] 2 3 046e 48 41.8 56.4 2 5 04ac 48 37.7 66.1 2 7 04ea 48 34.3 79.9 3 3 066d 48 39.6 60.9 3 5 06aa 48 34.3 79.9 4 3 086c 48 37.7 66.1 5 3 0a6b 48 35.9 72.3 6 3 0c6a 48 34.3 79.9 7 3 0e69 48 32.8 89.1 [1] 1 3 026f 44 40.6 48.1 1 5 02ae 44 38.4 51.6 1 7 02ed 44 36.4 55.7 1 9 032c 44 34.6 60.4 1 11 036b 44 33 66.1 1 13 03aa 44 31.5 73 1 15 03e9 44 30.1 81.4 [1] 2 3 046e 44 38.4 51.6 2 5 04ac 44 34.6 60.4 2 7 04ea 44 31.5 73 2 9 0528 44 28.9 92.1 [1]
mb91460k series document number: 002-04602 rev. *a page 62 of 86 86 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] remarks 3 3 066d 44 36.4 55.7 3 5 06aa 44 31.5 73 4 3 086c 44 34.6 60.4 4 5 08a8 44 28.9 92.1 [1] 5 3 0a6b 44 33 66.1 6 3 0c6a 44 31.5 73 7 3 0e69 44 30.1 81.4 [1] 8 3 1068 44 28.9 92.1 [1] 1 3 026f 40 37 43.6 1 5 02ae 40 34.9 46.8 1 7 02ed 40 33.1 50.5 1 9 032c 40 31.5 54.8 1 11 036b 40 30 59.9 1 13 03aa 40 28.7 66.1 1 15 03e9 40 27.4 73.7 2 3 046e 40 34.9 46.8 2 5 04ac 40 31.5 54.8 2 7 04ea 40 28.7 66.1 2 9 0528 40 26.3 83.3 [1] 3 3 066d 40 33.1 50.5 3 5 06aa 40 28.7 66.1 3 7 06e7 40 25.3 95.8 [1] 4 3 086c 40 31.5 54.8 4 5 08a8 40 26.3 83.3 [1] 5 3 0a6b 40 30 59.9 6 3 0c6a 40 28.7 66.1 7 3 0e69 40 27.4 73.7 8 3 1068 40 26.3 83.3 [1] 9 3 1267 40 25.3 95.8 [1] 1 3 026f 36 33.3 39.2 1 5 02ae 36 31.5 42 1 7 02ed 36 29.9 45.3 1 9 032c 36 28.4 49.2 1 11 036b 36 27.1 53.8 1 13 03aa 36 25.8 59.3
mb91460k series document number: 002-04602 rev. *a page 63 of 86 86 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] remarks 1 15 03e9 36 24.7 66.1 2 3 046e 36 31.5 42 2 5 04ac 36 28.4 49.2 2 7 04ea 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066d 36 29.9 45.3 3 5 06aa 36 25.8 59.3 3 7 06e7 36 22.8 85.8 [1] 4 3 086c 36 28.4 49.2 4 5 08a8 36 23.7 74.7 5 3 0a6b 36 27.1 53.8 6 3 0c6a 36 25.8 59.3 7 3 0e69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 [1] 1 3 026f 32 29.7 34.7 1 5 02ae 32 28 37.3 1 7 02ed 32 26.6 40.2 1 9 032c 32 25.3 43.6 1 11 036b 32 24.1 47.7 1 13 03aa 32 23 52.5 1 15 03e9 32 22 58.6 2 3 046e 32 28 37.3 2 5 04ac 32 25.3 43.6 2 7 04ea 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 [1] 3 3 066d 32 26.6 40.2 3 5 06aa 32 23 52.5 3 7 06e7 32 20.3 75.9 4 3 086c 32 25.3 43.6 4 5 08a8 32 21.1 66.1 5 3 0a6b 32 24.1 47.7 5 5 0aa6 32 19.5 89.1 [1] 6 3 0c6a 32 23 52.5
mb91460k series document number: 002-04602 rev. *a page 64 of 86 86 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] remarks 7 3 0e69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 [1] 1. these settings are not possible at mb91f465kx
mb91460k series document number: 002-04602 rev. *a page 65 of 86 86 15. electrical characteristics 15.1 absolute maximum ratings use within recommended operating conditions. use with dc voltage (current). b signals are input signals that exceed the v dd 5 voltage. ? b signals should always be applied by connec ting a limiting resistor between the ? b signal and the microcontroller. parameter symbol rating unit remarks min max power supply slew rate -- 50 v/ms power supply voltage 1 [1] v dd 5r ? 0.3 ? 6.0 v power supply voltage 2 [1] v dd 5 ? 0.3 ? 6.0 v relationship of the supply voltages av cc 5 v dd 5-0.3 v dd 5+0.3 v at least one pin of the ports 25 to 29 (ann) is used as digital input or output v ss 5-0.3 v dd 5+0.3 v all pins of the ports 25 to 29 (ann) follow the condition of v ia analog power supply voltage [1] 1. the parameter is based on v ss 5 ? av ss 5 ? 0.0 v. av cc 5 ? 0.3 ? 6.0 v [2] 2. av cc 5 and avrh5 must not exceed v dd 5 ? 0.3 v analog reference power supply voltage [1] avrh5 ? 0.3 ? 6.0 v [2] input voltage 1 [1] v i1 vss5 ? 0.3 v dd 5 ? 0.3 v analog pin input voltage [1] v ia avss5 ? 0.3 avcc5 ? 0.3 v output voltage 1 [1] v o1 vss5 ? 0.3 v dd 5 ? 0.3 v maximum clamp current i clamp ? 4.0 ? 4.0 ma [3] 3. total maximum clamp current ??? i clamp ? - 20 ma [3] ?l? level maximum output current [4] i ol - 10 ma ?l? level average output current [5] i olav - 8ma ?l? level total maximum output current ? i ol - 100 ma ?l? level total average output current [6] ? i olav - 50 ma ?h? level maximum output current [4] i oh - ? 10 ma ?h? level average output current [5] i ohav - ? 4ma ?h? level total maximum output current ? i oh - ? 100 ma ?h? level total average output current [6] ? i ohav - ? 25 ma power consumption p d - 500 mw at t a = 105c operating temperature t a ? 40 ? 105 c storage temperature tstg ? 55 ? 150 c
mb91460k series document number: 002-04602 rev. *a page 66 of 86 86 the value of the limiting resistor should be set so that the cu rrent input to the microcontroller pin does not exceed the rated value at any time , either instantaneously or for an extended period , when the ? b signal is input note that when the microcontroller drive current is lo w, such as in the low power consumption modes, the ? b input potential can increase the potential at the power supply pin via a protective diode, possibly affe cting other devices. note that if the ? b signal is input when the microcontroller is off (not fixed at 0 v), power is suppli ed through the +b input pin; therefore, th e microcontroller may partially operate. note that if the ? b signal is input at power-on, since the pow er is supplied through the pin, the power-on reset may not function in the power su pply voltage. do not leave ? b input pins open. example of recommended circuit : 4. maximum output current is defined as the value of t he peak current flowing through any one of the corresponding pins 5. average output current is defined as the value of the aver age current flowing through any one of the corresponding pins for a 100 ms period. 6. total average output current is defined as the value of the average current flowing through al l of the corresponding pins fo r a 100 ms period. warning: semiconductor devices can be permanently damaged by applic ation of stress (voltage, cu rrent, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r input/output equivalent circuit ? b input (0 v to 16 v) limiting resistor protective diode
mb91460k series document number: 002-04602 rev. *a page 67 of 86 86 15.2 recommended operating conditions ( v ss 5 ? av ss 5 ? 0.0 v ) warning: the recommended operating conditions ar e required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics ar e warranted when the device is operated within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditi ons, or combinations not re presented on the data sheet. users considering application outside the listed conditions are advised to contact thei r representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v dd 53.0 - 5.5 v v dd 5r 3.0 - 5.5 v internal regulator av cc 53.0 - 5.5 v a/d converter smoothing capacitor at vcc18c pin c s - 4.7 - ? f use a x7r ceramic capacitor or a capac- itor that has similar frequency characteristics. power supply slew rate -- 50 v/ms operating temperature t a ? 40 - ? 105 c main oscillation stabilisation time 10 ms lock-up time pll (4 mhz ->16 ...100mhz) 0.6 ms esd protection (human body model) v surge 2kv r discharge = 1.5k ? c discharge = 100pf rc oscillator f rc100khz 50 100 200 khz vdd core 1.65v f rc2mhz 124mhz c s avss5 vss5 vcc18c
mb91460k series document number: 002-04602 rev. *a page 68 of 86 86 15.3 dc characteristics note : in the following tables, ?v dd ? means v dd 5 for all pins. in the following tables, ?v ss ? means v ss 5 for all pins. ( v dd 5 ? av cc 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) parameter symbol pin name condition value unit remarks min typ max input ?h? voltage v ih - port inputs if cmos hysteresis 0.8/0.2 input is selected 0.8 ??? v dd - v dd ? 0.3 v cmos hysteresis input - port inputs if cmos hysteresis 0.7/0.3 input is selected 0.7 ?? v dd - v dd ? 0.3 v 4.5 v ? v dd ? 5.5 v 0.74 ?? v dd - v dd ? 0.3 v 3 v ? v dd < 4.5 v - automotive hystere- sis input is selected 0.8 ?? v dd - v dd ? 0.3 v - port inputs if ttl input is selected 2.0 - v dd ? 0.3 v v ihr initx - 0.8 ?? v dd - v dd ? 0.3 v initx input pin (cmos hysteresis) v ihm md_2 to md_0 - v dd ? 0.3 - v dd ? 0.3 v mode input pins v ihx0s x0, x0a - 2.5 - v dd ? 0.3 v external clock in ?oscillation mode? v ihx0f x0 - 0.8 ?? v dd - v dd ? 0.3 v external clock in ?fast clock input mode? input ?l? voltage v il - port inputs if cmos hysteresis 0.8/0.2 input is selected v ss ? 0.3 - 0.2 ?? v dd v - port inputs if cmos hysteresis 0.7/0.3 input is selected v ss ? 0.3 - 0.3 ?? v dd v - port inputs if automotive hysteresis input is se- lected v ss ? 0.3 - 0.5 ?? v dd v 4.5 v ? v dd ? 5.5 v v ss ? 0.3 - 0.46 ?? v dd v3 v ? v dd < 4.5 v - port inputs if ttl input is selected v ss ? 0.3 - 0.8 v v ilr initx - v ss ? 0.3 - 0.2 ?? v dd v initx input pin (cmos hysteresis) v ilm md_2 to md_0 - v ss ? 0.3 - v ss ? 0.3 v mode input pins v ilxds x0, x0a - v ss ? 0.3 - 0.5 v external clock in ?oscillation mode?
mb91460k series document number: 002-04602 rev. *a page 69 of 86 86 ( v dd 5 ? av cc 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) parameter symbol pin name condition value unit remarks min typ max input ?l? voltage v ilxdf x0 - v ss ? 0.3 - 0.2 ?? v dd v external clock in ?fast clock input mode? output ?h? voltage v oh2 normal outputs 4.5v v dd 5.5v, i oh ? ? 2ma v dd ? 0.5 -- v driving strength set to 2 ma 3.0v v dd 4.5v, i oh ? ? 1.6ma v oh5 normal outputs 4.5v v dd 5.5v, i oh ? ? 5ma v dd ? 0.5 -- v driving strength set to 5 ma 3.0v v dd 4.5v, i oh ? ? 3ma v oh3 i 2 c outputs 3.0v v dd 5.5v, i oh ? ? 3ma v dd ? 0.5 -- v output ?l? voltage v ol2 normal outputs 4.5v v dd 5.5v, i ol ? ? 2ma -- 0.4 v driving strength set to 2 ma 3.0v v dd 4.5v, i ol ? ? 1.6ma v ol5 normal outputs 4.5v v dd 5.5v, i ol ? ? 5ma -- 0.4 v driving strength set to 5 ma 3.0v v dd 4.5v, i ol ? ? 3ma v ol3 i 2 c outputs 3.0v v dd 5.5v, i ol ? ? 3ma -- 0.4 v input leakage current i il pnn_m [1] 1. pnn_m includes all gpio pins. analog (a n) channels and pull-up/pull-down are disabled. 3.0v v dd 5.5v t a =25 ? c ? 1 - ? 1 ? a v ss 5 < v i < v dd 3.0v v dd 5.5v t a =105 ? c ? 3 - ? 3 ? a analog input leakage current i ain ann [2] 2. ann includes all pins where an channels are enabled. 3.0v v dd 5.5v t a =25 ? c ? 1 - ? 1 ? a av ss 5 < v i < av cc 5, avrh5 3.0v v dd 5.5v t a =105 ? c ? 3 - ? 3 ? a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
mb91460k series document number: 002-04602 rev. *a page 70 of 86 86 ( v dd 5 ? av cc 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) parameter symbol pin name condition value unit remarks min typ max pull-up resistance r up pnn_m [1] initx 1. pnn_m includes all gpio pins. the pull up resistors must be e nabled by pper/ppcr setting and the pins must be in input direct ion. 3.0v v dd 3.6v 40 100 160 k ? 4.5v v dd 5.5v 25 50 100 pull-down resistance r down pnn_m [2] 2. pnn_m includes all gpio pins. the pull down resistors must be enabled by pper/ppcr setting and the pins must be in input direction. 3.0v v dd 3.6v 40 100 180 k ? 4.5v v dd 5.5v 25 50 100 input capacitance c in all except v dd 5, v dd 5r, v ss 5, av cc 5, av ss 5, avrh5 f ? 1 mhz - 5 15 pf power supply current mb91f-465kx i cc v dd 5r clkb: 80 mhz clkp: 40 mhz clkt: 40 mhz clkcan: 40 mhz - 80 90 ma code fetch from flash i cch v dd 5r t a ? ? 25c - 30 150 ? a at stop mode [3] 3. main regulator off, sub regulator se t to 1.2v, low voltage detection disabled. t a ? ? 105c - 400 2000 ? a t a ? ? 25c - 100 500 ? a rtc : 4 mhz mode [3] t a ? ? 105c - 500 2400 ? a t a ? ? 25c - 50 250 ? a rtc : 100 khz mode [3] 32 khz mode [4 ] 4. main regulator off, sub regulator set to 1.2v, low voltage detection disabled, rc oscillator enabled. additional current consum ption of sub oscillator iosc has to be taken into account t a ? ? 105c - 450 2200 ? a i lve v dd 5 -- 70 150 ? a external low voltage detection i lvi v dd 5r -- 50 100 ? a internal low voltage detection i osc v dd 5 -- 250 500 ? a main clock (4 mhz) -- 20 40 ? a sub clock (32 khz) ? ? ? ? ? ? ? ?
mb91460k series document number: 002-04602 rev. *a page 71 of 86 86 15.4 a/d converter characteristics ( v dd 5 ? av cc 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) note : the accuracy gets worse as avrh - avrl becomes smaller parameter symbol pin name value unit remarks min typ max resolution -- - - 10 bit total error -- ? 3 - ? 3lsb nonlinearity error -- ? 2.5 - ? 2.5 lsb differential nonlinearity error -- ? 1.9 - ? 1.9 lsb zero reading voltage v ot ann avrl ? 1.5 lsb avrl ? 0.5 lsb avrl ? 2.5 lsb v full scale reading voltage v fst ann avrh ? 3.5 lsb avrh ? 1.5 lsb avrh ? 0.5 lsb v compare time t comp - 0.6 - 16,500 ? s 4.5 v ? av cc 5 ? 5.5 v 2.0 -- ? s 3.0 v ? av cc 5 ? 4.5 v sampling time t samp - 0.4 -- ? s 4.5 v ? av cc 5 ? 5.5 v, r ext < 2 k ? 1.0 -- ? s 3.0 v ? av cc 5 ? 4.5 v, r ext < 1 k ? conversion time t conv - 1.0 -- ? s 4.5 v ? av cc 5 ? 5.5 v 3.0 -- ? s 3.0 v ? av cc 5 ? 4.5 v input capacitance c in ann -- 11 pf input resistance r in ann -- 2.6 k ? 4.5 v ? av cc 5 ? 5.5 v -- 12.1 k ? 3.0 v ? av cc 5 ? 4.5 v analog input leakage current i ain ann ? 1 - ? 1 ? at a ? ? 25c ? 3 - ? 3 ? at a ? ? 105c analog input voltage range v ain ann avrl - avrh v offset between input channels - ann -- 4lsb
mb91460k series document number: 002-04602 rev. *a page 72 of 86 86 sampling time calculation t samp = ( 2.6 kohm + r ext ) ?? 11pf ?? 7; for 4.5v ? av cc 5 ? 5.5v t samp = (12.1 kohm + r ext ) ?? 11pf ?? 7; for 3.0v ? av cc 5 ? 4.5v conversion time calculation t conv = t samp + t comp parameter symbol pin name value unit remarks min typ max reference voltage range avrh avrh5 0.75 ?? av cc 5 - av cc 5v avrl av ss 5av ss 5 - av cc 5 ?? 0.25 v power supply current i a av cc 5 - 2.5 5 ma a/d converter active i ah av cc 5 -- 5 ? a a/d converter not operated [1] 1. supply current at av cc 5, if the a/d converter is not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) reference voltage current i r avrh5 - 0.7 1 ma a/d converter active i rh avrh5 -- 5 ? a a/d converter not operated [2] 2. input current at avrh5, if a/d converter is not operating, (v dd 5 = av cc 5 = avrh = 5.0 v)
mb91460k series document number: 002-04602 rev. *a page 73 of 86 86 15.4.1 definition of a/d converter terms resolution analog variation that is recognizable by the a/d converter. nonlinearity error deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000 b ? 00 0000 0001 b ) and the full scale transition point (11 1111 1110 b ? 11 1111 1111 b ). differential nonlinearity error deviation of the input voltage from the ideal value that is required to change the output code by 1 lsb. total error this error indicates the difference between actual and theoretical values, including the zero transition erro r, full scale tra nsition error, and nonlinearity error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh 0.5 lsb' {1 lsb? (n - 1) + 0.5 lsb?} 1.5 lsb? analog input total error digital output actual conversion characteristics v nt ( measurement value) ideal characteristics actual conversion characteristics total error of digital output n ? 1 lsb' v nt ? {1 lsb' ? (n ? 1) ? 0.5 lsb'} n: a/d converter digital output value v ot ' (ideal value) ? av ss 5 ? 0.5 lsb' [v] v fst ' (ideal value) ? avrh ? 1.5 lsb' [v] v nt : voltage at which the digita l output changes from (n ? 1) h to n h 1lsb' (ideal value) ? 1024 avrh ? av ss 5 [v]
mb91460k series document number: 002-04602 rev. *a page 74 of 86 86 (n+1) h n h (n-1) h (n-2) h av ss 5 avrh 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh {1 lsb (n - 1) + v ot } analog input analog input differential nonlinearity error nonlinearity error digital output digital output actual conversion characteristics v fst (measure- ment value) v nt (measure- ment value) actual conversion characteristics ideal characteristics v to (measurement value) actual conversion characteristics v nt (measure- ment value) v fst (measure- ment value) nonlinearity error of digital output n ? 1lsb v nt ? {1lsb ?? (n ? 1) ? v ot } [lsb] differential nonlinearity error of digital output n ? 1lsb v ( n ? 1 ) t ? v nt ? 1 [lsb] 1lsb ? 1022 v fst ? v ot [v] n: a/d converter digital output value v ot : voltage at which the digital output changes from 000 h to 001 h . v fst : voltage at which the digital output changes from 3fe h to 3ff h . actual conversion characteristics ideal characteristics
mb91460k series document number: 002-04602 rev. *a page 75 of 86 86 15.5 flash memory program/erase characteristics 15.5.1 mb91f465kx (t a = 25 o c, vcc = 5.0v) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the number of flash sector of the device word (16-bit width) program- ming time - 23 370 ? s system overhead time not included programme/erase cycle 10 000 cycle flash data retention time 20 year [1] 1. this value was converted from the resu lts of evaluating the reliability of the te chnology (using arrhenius equation to conver t high temperature measurements into normalized value at 85 o c)
mb91460k series document number: 002-04602 rev. *a page 76 of 86 86 15.6 ac characteristics 15.6.1 clock timing ( v dd 5 ? 3.0 v to 5.5 v , vss5 ? avss5 ? 0 v , t a ? ? 40c to ? 105c ) figure 1. clock timing condition 15.6.2 reset input ratings ( v dd 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) parameter symbol pin name value unit condition min typ max clock frequency f c x0 x1 3.5 4 16 mhz opposite phase external supply or crystal x0a x1a 32 32.768 100 khz parameter symbol pin name condition value unit min max initx input time(at power-on) t intl initx - 10 - ms initx input time(other than the above) 20 - ? s 0.8 v cc 0.2 v cc p wh p wl t c x0, x1, x0a, x1a 0.2 v cc t intl initx
mb91460k series document number: 002-04602 rev. *a page 77 of 86 86 15.6.3 lin-usart timings at v dd 5 = 3.0 to 5.5 v conditions during ac measurements all ac tests were measured under the following conditions: ? - io drive = 5 ma ? - v dd 5 = 3.0 v to 5.5 v, i load = 3 ma ? - v ss 5 = 0 v ? - t a = -40c to +105c ? - c l = 50 pf (load capacity value of pins when testing) ? - v ol = 0.2 x v dd 5 ? - v oh = 0.8 x v dd 5 ? - epilr = 0, pilr = 1 (automotive level == worst case) ( v dd 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) if t scyci ? 2*k*t clkp , then m ? k, where k is an integer > 2 if t scyci ? (2*k ? 1)*t clkp , then m ? k ? 1, where k is an integer > 1 notes : the above values are ac characteristics for clk synchronous mode. t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition v dd 5 ? 3.0 v to 4.5 v v dd 5 ? 4.5 v to 5.5 v unit min max min max serial clock cycle time t scyci sckn internal clock operation (master mode) 4 t clkp - 4 t clkp - ns sck sot delay time t slovi sckn sotn ? 30 30 ? 20 20 ns sot sck delay time t ovshi sckn sotn m ?? t clkp ? 30 [1] - m ?? t clkp ? 20 [1] 1. parameter m depends on t scyci and can be calculated as : - ns valid sin ? sck setup time t ivshi sckn sinn t clkp ? 55 - t clkp ? 45 - ns sck ? valid sin hold time t shixi sckn sinn 0 - 0 - ns serial clock ?h? pulse width t shsle sckn external clock operation (slave mode) t clkp ? 10 - t clkp ? 10 - ns serial clock?l? pulse width t slshe sckn t clkp ? 10 - t clkp ? 10 - ns sck ? sot delay time t slove sckn sotn - 2 t clkp ? 55 - 2 t clkp ? 45 ns valid sin ? sck setup time t ivshe sckn sinn 10 - 10 - ns sck ? valid sin hold time t shixe sckn sinn t clkp ? 10 - t clkp ? 10 - ns sck rising time t fe sckn - 20 - 20 ns sck falling time t re sckn - 20 - 20 ns
mb91460k series document number: 002-04602 rev. *a page 78 of 86 86 figure 2. internal clock mode (master mode) figure 3. external clock mode (slave mode) t ivshi v ih t shixi t slovi t scyci v ol sotn sckn for escr:sces = 0 sckn for escr:sces = 1 t ovshi v ol v ol v il v ol v il v ih v oh v oh v oh v oh sinn t ivshe v ih t shixe t slove t slshe v ol sotn sckn for escr:sces = 0 sckn for escr:sces = 1 v ol v il v ol v il v ih v oh v oh v ol v oh v oh v oh sinn t shsle v ol t re v oh t fe v ol
mb91460k series document number: 002-04602 rev. *a page 79 of 86 86 15.6.4 i 2 c ac timings at v dd 5 = 3.0 to 5.5 v conditions during ac measurements all ac tests were measured under the following conditions: ? -io drive ? 3 ma ? -v dd 5 ? 3.0 v to 5.5 v, i load ? 3 ma ? -v ss 5 ? 0 v ? -t a ? ? 40c to ? 105c ? -c l ? 50 pf ? -v ol ? 0.3 ?? v dd 5 ? -v oh ? 0.7 ?? v dd 5 ? -epilr ? 0, pilr ? 0 (cmos hysteresis v il /v ih = 0.3 ?? v dd 5/0.7 ?? v dd 5) 15.6.4.1 fast mode: ( v dd 5 ? 3.5 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) note: t clkp is the cycle time of the peripheral clock. parameter symbol pin name value unit remark min max scl clock frequency f scl scln 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta scln, sdan 0.6 - ? s low period of the scl clock t low scln 1.3 - ? s high period of the scl clock t high scln 0.6 - ? s setup time for a repeated start condition t su;sta scln, sdan 0.6 - ? s data hold time for i 2 c-bus devices t hd;dat scln, sdan 0 0.9 ? s data setup time t su;dat scln sdan 100 - ns rise time of both sda and scl signals t r scln, sdan 20 + 0.1cb 300 ns fall time of both sda and scl signals t f scln, sdan 20 + 0.1cb 300 ns setup time for stop condition t su;sto scln, sdan 0.6 - ? s bus free time between a stop and start condition t buf scln, sdan 1.3 - ? s capacitive load for each bus line c b scln, sdan - 400 pf pulse width of spike suppressed by input fil- ter t sp scln, sdan 0 (1..1.5) ?? t clkp ns [1] 1. the noise filter will suppress single spikes with a pulse width of 0ns and betw een (1 to 1.5) cycles of peripheral clock, dep ending on the phase relationship between i 2 c signals (sda, scl) and peripheral clock.
mb91460k series document number: 002-04602 rev. *a page 80 of 86 86 sda s sr p s scl t hd;sta tr tr t sp t su;st0 t su;sta t su;dat t hd;dat t hd;sta t low t high t buf tf tf
mb91460k series document number: 002-04602 rev. *a page 81 of 86 86 15.6.5 free-run timer clock (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40c to ? 105c) note: t clkp is the cycle time of the peripheral clock. 15.6.6 trigger input timing ( v dd 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40c to ? 105c ) note: t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition value unit min max input pulse width t tiwh t tiwl ckn - 4t clkp - ns parameter symbol pin name condition value unit min max input capture input trigger t inp icun - 5t clkp - ns a/d converter trigger t atgx atgx - 5t clkp - ns t tiwh t tiwl ckn icun, atgx t atgx, t inp
mb91460k series document number: 002-04602 rev. *a page 82 of 86 86 16. ordering information part number package remarks mb91f465kapmt-gse2 120-pin plastic lqfp (fpt-120p-m21) not recommended MB91F465KBPMT-GSE2 lead-free package
mb91460k series document number: 002-04602 rev. *a page 83 of 86 86 17. package dimension 120-pin pla s tic lqfp lead pitch 0.50 mm package width package length 16.0 16.0 mm lead s hape g u llwing sealing method pla s tic mold mo u nting height 1.70 mm max weight 0.88 g code (reference) p-lfqfp120-16 16-0.50 120-pin pla s tic lqfp (fpt-120p-m21) (fpt-120p-m21) c 2002 fujitsu limited f120033s-c-4-4 1 30 60 31 90 61 120 91 sq 18.000.20(.709.008)sq 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) index .006 ?.001 +.002 ?0.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?.004 +.008 ?0.10 +0.20 1.50 detail s of "a" part (mo u nting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0~8 ? * .630 ?.004 +.016 ?0.10 +0.40 16.00 dimen s ion s in mm (inche s ). note: the val u e s in parenthe s e s are reference val u e s . ?2002-2008 fujitsu microelectronics limited f120033s-c-4-5 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010) max(each s ide). note 2) pin s width and pin s thickne ss incl u de plating thickne ss . note 3) pin s width do not incl u de tie bar c u tting remainder.
mb91460k series document number: 002-04602 rev. *a page 84 of 86 86 18. main changes in this edition spansion publication number: ds07-16606-2e note: please see ?document history? for later revised information. page section change results 4 product lineup technology in ? m instead of um 4 product lineup temteratur --> temperature 6 pin assignment removed the quadratic index mark on upper left corner,renamed "frckn" into "ckn" (n=0 to 7) 10 pin description; power supply/ground pins renamed "gnd" into "ground" 18 handling devices; power supply pins corrected "capacitator" into ?capacitor? 21 block diagram renamed "rtc" into "real time cl ock?,general purpose io ports: added "without resource" 23 programming model renamed program status register into "ps" (instead of rs) 28 flash memory map mb91f465kx changed unit "kb" into "kb" 38 i/o map address 00010ch added address 00010ch (reserved) 45 i/o map address 0004c0h changed ?can (clock control)? into ?can clock control? 49 io map after address 7010 h changed the start address of the reserved area after 007010 h to 007014h 53 i/o map; flash memory and external bus area corrected table header (added "+0 +1 +2 +3" ) 60 recommended settings; clock modulator settings removed all settings for baseclk > 48 mhz 67 recommended operating conditions corrected "look -up time pll" into "lock-up time pll" 69 dc characteristics; output "l" voltage corrected condition i oh into i ol 70 dc characteristics; table foot note changed ?p ullup/pulldown? into ?pull-up/pull-down? 70 dc characteristics; icch icch (rtc mode) at 32khz is similar to 100khz, footnote added 71 a/d converter characteristics; zero reading voltage, full scale reading voltage corrected values into ?value +- n lsb ?and unit into ?v? (volt) 76 ac characteristics; reset input ratings initx at power-on min. 10ms (accordi ng to the main oscillation stabil- isation time) 5,76,78 ambient temperature changed the symbol of ambient temperature from ta into t a 76,78 ac characteristics; lin ac timings i2c ac timings corrected condition vol into v ol , voh into v oh 79 ac characteristics; i 2 c ac timings corrected epilr,pilr conditi on into "cmos hysteresis vil/vih =..." 82 package dimension corrected the link to package web page,updated package drawing (latest formatting only)
mb91460k series document number: 002-04602 rev. *a page 85 of 86 86 document history document title: mb91f465ka, mb91f465kb, fr60 mb91460k series, 32-bit microcontroller datasheet document number: 002-04602 revision ecn orig. of change submission date description of change ** ? akih 11/11/2009 migrated to cypress and assigned document number 002-04602. no change to document contents or format. *a 5200604 akih 04/11/2016 updated to cypress template
document number: 002-04602 rev. *a revised april 14, 2016 page 86 of 86 mb91460k series ? cypress semiconductor corporation 2009-2016. this document is the property of cypress semiconductor corporation and its subsi diaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of an y product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly d esign, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support de vices or systems, other medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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